Processor with efficient arithmetic units

Patent metadata

Field	Value
Publication number	US-10929101-B2
Application number	US-201816056115-A
Country	US
Kind code	B2
Filing date	Aug 6, 2018
Priority date	Aug 23, 2013
Publication date	Feb 23, 2021
Grant date	Feb 23, 2021

Abstract

A processor includes a carry save array multiplier. The carry save array multiplier includes an array of cascaded partial product generators. The array of cascaded partial product generators is configured to generate an output value as a product of two operands presented at inputs of the multiplier. The array of cascaded partial product generators is also configured to generate an output value as a sum of two operands presented at inputs of the multiplier.

First claim

What is claimed is:

1. A processor, comprising:
a multiplier having a first input, a second input, and an output;
an arithmetic logic unit (ALJ) having:
an adder having a first input, a second input, a third input, and an output, the adder configured to receive a first operand at the first input of the adder and a second operand at the second input of the adder;
a carry register having an input and an output, the input of the carry register coupled to the output of the adder; and
a multiplexer having a first input, a second input, a third input, and an output, the first input of the multiplexer coupled to the output of the carry register and the output of the multiplexer coupled to the third input of the adder;

a first register having an input and output, the input of the first register coupled to the output of the multiplier and the output of the adder, the output of the first register coupled to the first input of the multiplier, the first input of the adder, and the second input of the multiplexer;
a second register having an input and an output, the input of the second register coupled to the output of the multiplier and the output of the adder, the output of the second register coupled to the second input of the multiplier, the second input of the adder, and the third input of the multiplexer; and
a sequencing logic coupled to control the multiplier, the ALU, the first register and the second register.

2. The processor of claim 1 , wherein the adder has a second output, and the second output of the adder is configured to output a sum value.

3. The processor of claim 2 , wherein the second output of the adder is configured to output a single-precision sum value at a first execution cycle and a double-precision sum value at a second execution cycle.

4. The processor of claim 1 , wherein the first output of the adder is configured to output a carry out value.

5. The processor of claim 1 , wherein the sequencing logic is configured to control the ALU to selectably perform addition or subtraction, and is configured to control the multiplier and the ALU to selectably perform a single precision multiply and accumulate (MAC) or a double precision MAC.

Assignees

• Texas Instruments Inc

Inventors

• Wiencke Christian
• Stingl Armin

Classifications

• G06F7/5324 Primary

  partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers · CPC title

• G06F7/42

  Adding; Subtracting {(G06F7/405 takes precedence)} · CPC title

• G06F7/44 Primary

  Multiplying; Dividing {(G06F7/405 takes precedence)} · CPC title