Data storage system with I/O determinism latency optimization

Patent metadata

Field	Value
Publication number	US-10929025-B2
Application number	US-201916451841-A
Country	US
Kind code	B2
Filing date	Jun 25, 2019
Priority date	Jun 25, 2019
Publication date	Feb 23, 2021
Grant date	Feb 23, 2021

Abstract

In a data storage system, latency optimization can be practiced by logging a plurality of data accesses to a memory in a register with each data access of the plurality of data accesses corresponding with a command generated by a host connected to the memory. The register may be analyzed with a system module to predict a command execution latency value for the plurality of data accesses that can be used to generate a deterministic data access sequence with the system module. A queue of data accesses can then be reorganized from a first sequence to the deterministic data access sequence to reduce command execution latency variability during a deterministic window selected by the host.

First claim

What is claimed is:

1. A method comprising:
logging a plurality of data accesses to a memory in a register, each data access of the plurality of data accesses corresponding with a command generated by a host connected to the memory;
analyzing the register with a system module to identify an actual system operational parameter;
generating a deterministic strategy with the system module in response to the identified actual system operational parameter, the deterministic strategy providing a deterministic data access sequence; and
reorganizing a queue of data accesses from a first sequence to the deterministic data access sequence while at least one of the plurality of data accesses are executed to the data storage device connected to the system module, the deterministic data access sequence configured to reduce command execution latency variability during a deterministic window selected by the host.

2. The method of claim 1 , wherein the first sequence and the deterministic data access sequence are different.

3. The method of claim 1 , wherein the reorganization of the queue is conducted proactively prior to execution of any of the plurality of data accesses stored in the queue.

4. The method of claim 1 , wherein the reorganization of the queue is conducted while each of the plurality of data accesses are executed to a data storage device connected to the system module.

5. The method of claim 1 , wherein the actual operational parameter is data read latency in a namespace connected to the system module where each of the plurality of data access requests are assigned.

6. The method of claim 1 , wherein the actual operational parameter is error rate in a namespace connected to the system module where each of the plurality of data access requests are assigned.

7. The method of claim 1 , wherein the deterministic window maintains a predetermined read latency between the host and a data storage device for a period of time determined by the system module.

8. The method of claim 1 , wherein a first controller of the system module reorganizes the queue while a second controller of the system module services data access requests in the deterministic window.

9. The method of claim 1 , wherein a first controller of the system module and a second controller of the system module concurrently reorganize the queue and service a plurality of data access requests of the deterministic window.

10. A method comprising:
logging a plurality of data accesses to a memory in a register, each data access of the plurality of data accesses corresponding with a command generated by a host connected to the memory;
analyzing the register with a system module to predict a command execution latency value for the plurality of data accesses;
generating a first deterministic data access sequence with the system module in response to the predicted command execution latency value; and
reorganizing a queue of data accesses from a first sequence to the first deterministic data access sequence to reduce command execution latency variability during a deterministic window selected by the host, the system module prescribing at least one proactive action to increase the availability and accuracy of data access request execution consistency during the deterministic window.

11. The method of claim 10 , wherein the command execution latency value is an average of an execution of the plurality of data accesses queued in the queue.

12. The method of claim 10 , wherein the system module evaluates one or more hypothetical sequences in response to the analysis of at least one operational parameter and the predicted future operational parameter of a data storage device connected to the system module.

13. The method of claim 10 , wherein the at least one proactive action is part of a deterministic strategy generated by the system module.

14. The method of claim 10 , wherein the deterministic window concurrently services more than one host connected to the system module.

15. The method of claim 10 , wherein the deterministic window concurrently services more than one namespace.

16. The method of claim 10 , wherein the system module proactively moves a pending data access request from the first cache to a second cache to reorganize the queue.

17. The method of claim 10 , wherein the system module generates a second deterministic data access sequence in response to a determination that the first deterministic data access sequence is not optimized to at least one detected operational parameter of a data storage device connected to the system module.

18. An apparatus comprising a system module connected to a host and a data storage device, the system module comprising a deterministic circuit configured to log a plurality of data accesses to the data storage device in a register with each data access of the plurality of data accesses corresponding with a command generated by a host connected to the memory, a first controller of the system module analyzes the register to identify an actual system operational parameter and generate a deterministic strategy in response to the identified actual system operational parameter, the actual operational parameter is error rate in a namespace connected to the system module where each of the plurality of data access requests are assigned, the deterministic strategy providing a deterministic data access sequence, a second controller of the system controller configured to reorganize a queue of data accesses from a first sequence to the deterministic data access sequence to reduce command execution latency variability during a deterministic window selected by the host.

19. The apparatus of claim 18 , wherein the system module comprises a polling circuit configured to monitor data access operations over time to identify multiple different operational characteristics of the data storage device to populate a log.

20. The apparatus of claim 18 , wherein the system controller is connected to multiple different namespaces of the data storage device.

Assignees

• Seagate Technology Llc

Inventors

• Shaw Michael

Classifications

• G06F3/0638

  Organizing or formatting or addressing of data · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0611 Primary

  in relation to response time · CPC title