Latency command processing for solid state drive interface protocol

Patent metadata

Field	Value
Publication number	US-9563367-B2
Application number	US-201414469225-A
Country	US
Kind code	B2
Filing date	Aug 26, 2014
Priority date	Aug 26, 2014
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

The present disclosure relates to methods, apparatuses, systems, and computer program products for processing commands for accessing solid state drives. Example methods can include receiving, from a host, a loaded command availability message. The loaded command availability message can indicate that a command associated with the loaded command availability message uses a low latency mode. The methods can further include executing the associated command.

First claim

What is claimed is:

1. A method of processing a command for accessing a solid state device, the method comprising:
receiving, from a host, a loaded command availability message, wherein the loaded command availability message indicates that a command associated with the loaded command availability message uses a low latency mode, wherein the loaded command availability message includes fields for:
direct memory access (DMA) information,
a logical block address (LBA),
a completion address,
security information, and a length; and

executing the associated command.

2. The method of claim 1 , further comprising:
processing a completion of the executed command without generating a traditional interrupt and without writing a completion entry to a normal completion queue on the host; and
upon receiving, from the host, a subsequent command, presuming an acknowledgement by the host of the processed completion.

3. The method of claim 1 , further comprising fetching at least one of remaining physical region pages (PRP) and remaining scatter gather lists (SGL) upon a condition that the at least one of the remaining PRP and the remaining SGL exist.

4. The method of claim 1 , wherein the receiving the loaded command availability message further comprises polling by a latency command processing module substantially periodically and retrieving a remainder of the loaded command availability message for execution.

5. The method of claim 1 , further comprising classifying the associated command as at least one of a latency class command and a compact class command.

6. The method of claim 1 , wherein the accessing the solid state drive is according to a non-volatile memory express (NVMe) standard modified for latency command processing.

7. A controller comprising:
an interface; and
at least one processor in communication with the interface, the processor configured for:
receiving, over the interface, a loaded command availability message, wherein the loaded command availability message indicates that a command associated with the loaded command availability message uses a low latency mode, wherein the loaded command availability message includes fields for:
direct access memory (DMA) information,
a logical block address(LBA),
a completion address,
security information, and a length; and

executing the associated command.

8. The controller of claim 7 , wherein the processor is further configured for:
processing a completion of the executed command without generating an interrupt and without writing a completion entry to a normal completion queue on the host; and
upon receiving, over the interface, a subsequent command, presuming an acknowledgement by the host of the processed completion.

9. The controller of claim 7 , wherein the processor is further configured for fetching at least one of remaining physical region pages (PRP) and remaining scatter gather lists (SGL) upon a condition that the at least one of the remaining PRP and the remaining SGL exist.

10. The controller of claim 7 , wherein the processor configured for receiving the loaded command availability message further comprises the processor configured for polling by a latency command processing module substantially periodically and retrieving a remainder of the loaded command availability message for execution.

11. The controller of claim 7 , wherein the processor is further configured for classifying the associated command as at least one of a latency class command and a compact class command.

12. A computer program product for processing a command for accessing a solid state device, the computer program product tangibly embodied in a non-transitory computer-readable medium, the computer program product including instructions operable to cause a data processing apparatus to:
receive a loaded command availability message, wherein the loaded command availability message indicates that a command associated with the loaded command availability message uses a low latency mode, wherein the loaded command availability message includes fields for:
direct access memory (DMA) information,
a logical block address(LBA),
a completion address,
security information, and a length;

execute the associated command;
process a completion of the executed command without generating an interrupt and without writing a completion entry to a completion queue on the host; and
upon receiving a subsequent command, presume an acknowledgement by the host of the processed completion.

13. The computer program product of claim 12 , further comprising instructions operable to cause the data processing apparatus to:
process a completion of the executed command without generating an interrupt and without writing a completion entry to a normal completion queue on the host; and
upon receiving a subsequent command, presume an acknowledgement by the host of the processed completion.

14. The computer program product of claim 12 , further comprising instructions operable to cause the data processing apparatus to fetch at least one of remaining physical region pages (PRP) and remaining scatter gather lists (SGL) upon a condition that the at least one of the remaining PRP and the remaining SGL exist.

15. The computer program product of claim 12 , wherein the instructions operable to cause the data processing apparatus to receive the loaded command availability message further comprise instructions operable to cause the data processing apparatus to poll using a latency command processing module substantially periodically and retrieve a remainder of the loaded command availability message for execution.

16. The computer program product of claim 12 , further comprising instructions operable to cause the data processing apparatus to classify the associated command as at least one of a latency class command and a compact class command.

17. The computer program product of claim 12 , wherein the computer program product for accessing the solid state device accesses the solid state device according to a non-volatile memory express (NVMe) standard modified for latency command processing.

Assignees

• HGST Netherlands BV

Inventors

• Chu Frank
• Bandic Zvonimir Z
• Vucinic Dejan
• Guyot Cyril
• Wang Qingbo

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0611 Primary

  in relation to response time · CPC title