Memory device

Patent metadata

Field	Value
Publication number	US-10923500-B2
Application number	US-201916360932-A
Country	US
Kind code	B2
Filing date	Mar 21, 2019
Priority date	Sep 19, 2018
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

A memory device according to an embodiment includes a first conductive layer, a second conductive layer, and a first layer provided between the first conductive layer and the second conductive layer and containing aluminum oxide that contains at least one first element selected from the group consisting of magnesium (Mg), silicon (Si), hafnium (Hf), tungsten (W), and ruthenium (Ru), and the aluminum oxide is a ferroelectric.

First claim

What is claimed is:

1. A memory device comprising:
a first conductive layer;
a second conductive layer; and
a first layer provided between the first conductive layer and the second conductive layer, the first layer including aluminum oxide, the aluminum oxide containing ruthenium (Ru), and the aluminum oxide being a ferroelectric.

2. The memory device according to claim 1 , wherein a thickness of the first layer is more than or equal to 1 nm and less than or equal to 15 nm.

3. The memory device according to claim 1 , wherein a c-axis direction of the aluminum oxide in the first layer is within a range of ±10° with respect to a direction from the first conductive layer to the second conductive layer.

4. The memory device according to claim 1 , further comprising a second layer provided between the first conductive layer and the first layer, the second layer containing at least one of oxide and oxynitride.

5. The memory device according to claim 1 , wherein the first conductive layer is a semiconductor layer.

6. A memory device comprising:
a first conductive layer;
a second conductive layer; and
a first layer provided between the first conductive layer and the second conductive layer, the first layer including aluminum oxide, the aluminum oxide containing at least one first element selected from the group consisting of magnesium (Mg), silicon (Si), hafnium (Hf), tungsten (W), and ruthenium (Ru), and the aluminum oxide being a ferroelectric,
wherein the aluminum oxide contains at least one second element selected from the group consisting of manganese (Mn), chromium (Cr), and cobalt (Co).

7. The memory device according to claim 6 , wherein the first conductive layer is a semiconductor layer.

8. A memory device comprising:
a first conductive layer;
a second conductive layer; and
a first layer provided between the first conductive layer and the second conductive layer, the first layer including aluminum oxide, the aluminum oxide containing at least one first element selected from the group consisting of magnesium (Mg), silicon (Si), hafnium (Hf), tungsten (W), and ruthenium (Ru), and the aluminum oxide being a ferroelectric,
wherein the aluminum oxide contains at least one second element selected from the group consisting of sulfur (S) and chlorine (Cl).

9. The memory device according to claim 8 , wherein the first conductive layer is a semiconductor layer.

10. A memory device comprising:
a first conductive layer;
a second conductive layer; and
a first layer provided between the first conductive layer and the second conductive layer, the first layer including aluminum oxide, the aluminum oxide containing ruthenium (Ru), and the aluminum oxide being κ (kappa)-aluminum oxide.

11. The memory device according to claim 10 , wherein a thickness of the first layer is more than or equal to 1 nm and less than or equal to 15 nm.

12. The memory device according to claim 10 , wherein a c-axis direction of the aluminum oxide in the first layer is within a range of ±10° with respect to a direction from the first conductive layer to the second conductive layer.

13. The memory device according to claim 10 , further comprising a second layer provided between the first conductive layer and the first layer, the second layer containing at least one of oxide and oxynitride.

14. The memory device according to claim 10 , wherein the first conductive layer is a semiconductor layer.

15. A memory device comprising:
a first conductive layer;
a second conductive layer; and
a first layer provided between the first conductive layer and the second conductive layer, the first layer including aluminum oxide, the aluminum oxide containing at least one first element selected from the group consisting of magnesium (Mg), silicon (Si), hafnium (Hf), tungsten (W), and ruthenium (Ru), the aluminum oxide being κ (kappa)-aluminum oxide,
wherein an a-axis length of the aluminum oxide is 97% or more and 99.5% or less of a standard a-axis length, and a b-axis length of the aluminum oxide is 97% or more and 99.5% or less of a standard b-axis length, the standard a-axis length and the standard b-axis length of the aluminum oxide being an a-axis length and a b-axis length of κ-aluminum oxide described in an International Center for Diffraction Data (ICDD) database.

16. The memory device according to claim 15 , wherein a c-axis direction of the aluminum oxide in the first layer is within a range of ±10° with respect to a direction from the first conductive layer to the second conductive layer.

17. The memory device according to claim 11 , wherein the first conductive layer is a semiconductor layer.

18. A memory device comprising:
a first conductive layer;
a second conductive layer; and
a first layer provided between the first conductive layer and the second conductive layer, the first layer including aluminum oxide, the aluminum oxide containing at least one first element selected from the group consisting of magnesium (Mg), silicon (Si), hafnium (Hf), tungsten (W), and ruthenium (Ru), and the aluminum oxide being κ (kappa)-aluminum oxide,
wherein the aluminum oxide contains at least one second element selected from the group consisting of manganese (Mn), chromium (Cr), and cobalt (Co).

19. The memory device according to claim 12 , wherein the first conductive layer is a semiconductor layer.

20. A memory device comprising:
a first conductive layer;
a second conductive layer; and
a first layer provided between the first conductive layer and the second conductive layer, the first layer including aluminum oxide, the aluminum oxide containing at least one first element selected from the group consisting of magnesium (Mg), silicon (Si), hafnium (Hf), tungsten (W), and ruthenium (Ru), and the aluminum oxide being κ (kappa)-aluminum oxide,
wherein the aluminum oxide contains at least one second element selected from the group consisting of sulfur (S) and chlorine (Cl).

21. The memory device according to claim 20 , wherein the first conductive layer is a semiconductor layer.

Assignees

• Toshiba Memory Corp

Inventors

• Ino Tsunehiro
• Kamimuta Yuuichi

Classifications

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• H10D64/689

  having ferroelectric layers · CPC title

• H01L27/11597

  Electricity · mapped topic

• H01L27/11507

  Electricity · mapped topic

• H01L27/2463

  Electricity · mapped topic