Semiconductor integrated circuit structure

Patent metadata

Field	Value
Publication number	US-10923481-B2
Application number	US-201816151323-A
Country	US
Kind code	B2
Filing date	Oct 3, 2018
Priority date	Sep 9, 2016
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

First claim

What is claimed is:

1. A semiconductor integrated circuit (IC) structure comprising:
a substrate comprising at least a memory cell region and a peripheral region defined thereon;
a plurality of memory cells formed in the memory cell region;
at least an active device formed in the peripheral region;
a plurality of contact plugs formed in the memory cell region, and bottom surfaces of the contact plugs being lower than a surface of the substrate; and
at least a bit line formed in the memory cell region, and the contact plugs being physically and electrically connected to the bit line, wherein the active device comprises:
at least a gate electrode; and
a gate dielectric layer disposed between the gate electrode and the substrate, wherein the gate electrode comprises a semiconductor layer directly contacting the gate dielectric layer, and a top surface of the semiconductor layer is coplanar with a top surface of the bit line.

2. The semiconductor IC structure according to claim 1 , wherein the memory cells comprise dynamic random access memory (DRAM) cells.

3. The semiconductor IC structure according to claim 1 , wherein a top surface of the gate electrode is coplanar with the top surface of the bit line.

4. The semiconductor IC structure according to claim 3 , wherein the bottom surfaces of the contact plugs are lower than a bottom surface of the gate electrode.

5. The semiconductor IC structure according to claim 3 , wherein the contact plugs and the bit line in the memory cell region and the gate electrode of the active device in the peripheral region comprise a same material.

6. The semiconductor IC structure according to claim 1 , wherein the bottom surfaces of the contact plugs are lower than a bottom surface of the gate dielectric layer.

7. The semiconductor IC structure according to claim 1 , wherein a topmost surface of the semiconductor layer is coplanar with a topmost surface of the bit line.

Assignees

• United Microelectronics Corp
• Fujian Jinhua Integrated Circuit Co Ltd

Inventors

• Li Yu-Ting
• Lin Jen-Chieh
• Lin Wen-Chin
• Huang Po-Cheng
• Tsai Fu-Shou

Classifications

• H10D84/0126

  the components including insulated gates, e.g. IGFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/00

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

• H01L27/10876

  Electricity · mapped topic

• H01L27/10894

  Electricity · mapped topic