Semiconductor device and a method of increasing a resistance value of an electric fuse

Patent metadata

Field	Value
Publication number	US-10923419-B2
Application number	US-201916547279-A
Country	US
Kind code	B2
Filing date	Aug 21, 2019
Priority date	Mar 7, 2006
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

A semiconductor device is provided which includes an interlayer dielectric formed on a semiconductor substrate, a first insulating layer, having a trench, formed on the interlayer dielectric, a barrier film formed on side and bottom surfaces of the first trench, an electric fuse formed on the barrier film, a second insulating layer formed to directly contact the electric fuse, and a third insulating layer formed on the second insulating layer. A linear expansion coefficient of the electric fuse is greater than a linear expansion coefficient of the first insulating layer and the second insulating layer, and a melting point of the barrier film is greater than a melting point of the electric fuse.

First claim

We claim:

1. A semiconductor device, comprising:
a semiconductor substrate;
a first insulator layer formed over the semiconductor substrate, the first insulator layer having a trench;
an electric fuse comprised of:
a main wiring formed in the trench; and
a barrier film covering a lower surface of the main wiring and side surfaces of the main wiring;

a second insulator layer formed on the first insulator layer such that the second insulator layer directly contacts with the main wiring; and
a third insulator layer formed on the second insulator layer,
wherein the second insulator layer is comprised of:
a first layer formed on the first insulator layer, the first layer being comprised of a first combination of materials; and
a second layer formed on the first layer, the second layer being comprised of a second combination of materials different than the first combination of materials, wherein the main wiring is comprised of:
a first portion; and
a second portion connected to the first portion, the second portion having a width larger than a width of the first portion in plan view;

wherein the first portion and the second portion are formed in the trench,
wherein a linear expansion coefficient of the main wiring is larger than a linear expansion coefficient of each of the first insulator layer and the first and second layer of the second insulator layer, and
wherein a melting point of the main wiring is lower than a melting point of each of the first insulator layer and the first and second layer of the second insulator layer.

2. The semiconductor device according to the claim 1 ,
wherein the second portion is formed in a same layer as the first portion.

3. The semiconductor device according to the claim 1 ,
wherein a linear expansion coefficient of the barrier film is smaller than the linear expansion coefficient of the main wiring, and is larger than the linear expansion coefficient of each of the first insulator layer and at least one of the first and second layers of the second insulator layer, and
wherein a melting point of the barrier film is higher than the melting point of the main wiring, and is lower than the melting point of each of the first insulator layer and the first and second layers of the second insulator layer.

4. The semiconductor device according to the claim 1 ,
wherein the main wiring is made of copper film.

5. The semiconductor device according to the claim 1 ,
wherein the first insulator layer has a dielectric constant of 3 or less.

6. The semiconductor device according to the claim 1 , further comprising, in cross-sectional view perpendicular to the first portion of the main wiring:
a first wiring formed above the first portion of the main wiring;
a second wiring formed below the first portion of the main wiring;
a third wiring formed such that the third wiring faces to a first side surface of the main wiring; and
a fourth wiring formed such that the fourth wiring faces to a second side surface of the main wiring.

7. The semiconductor device according to the claim 1 ,
wherein the main wiring is surrounded by a plurality of wirings and a plurality of vias in cross-sectional view perpendicular to the first portion of the main wiring.

8. The semiconductor device according to the claim 1 , wherein the electric fuse extends inside the trench.

9. The semiconductor device according to the claim 1 ,
wherein the main wiring is comprised of a third portion connected to the second portion, and
wherein the third portion has a width smaller than the width of the second portion in plan view.

10. The semiconductor device according to the claim 6 ,
wherein the main wiring is comprised of a third portion connected to the second portion, and
wherein the third portion has a width smaller than the width of the second portion in plan view.

11. The semiconductor device according to the claim 1 ,
wherein the main wiring is configured such that the first portion is cut by receiving a supply of an electrical current to the main wiring.

12. The semiconductor device according to the claim 10 ,
wherein the main wiring is configured such that the first portion is cut by receiving a supply of an electrical current to the main wiring.

13. The semiconductor device according to the claim 1 , wherein the electric fuse is arranged between a power source electrode and a ground electrode.

14. The semiconductor device according to the claim 13 , wherein a resistor is arranged between the electric fuse and the power source electrode.

15. The semiconductor device according to the claim 14 , further comprising:
a transistor; and
a decision circuit configured to detect whether or not a resistance of the electric fuse turns into a predetermined value or more,
wherein the transistor and the decision circuit are connected to a wiring between the resistor and the electric fuse.

16. The semiconductor device according to the claim 2 , wherein the first combination of materials comprises Si, C and N, and second combination of materials comprises Si and O.

Assignees

• Renesas Electronics Corp

Inventors

• Iwamoto Takeshi
• Kono Kazushi
• Arakawa Masashi
• Yonezu Toshiaki
• Obayashi Shigeki

Classifications

• H10W42/80 Primary

  protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/49

  Adaptable interconnections, e.g. fuses or antifuses · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title