Semiconductor device and a method of increasing a resistance value of an electric fuse

Patent metadata

Field	Value
Publication number	US-2019378796-A1
Application number	US-201916547279-A
Country	US
Kind code	A1
Filing date	Aug 21, 2019
Priority date	Mar 7, 2006
Publication date	Dec 12, 2019
Grant date	—

Abstract

A semiconductor device is provided which includes an interlayer dielectric formed on a semiconductor substrate, a first insulating layer, having a trench, formed on the interlayer dielectric, a barrier film formed on side and bottom surfaces of the first trench, an electric fuse formed on the barrier film, a second insulating layer formed to directly contact the electric fuse, and a third insulating layer formed on the second insulating layer. A linear expansion coefficient of the electric fuse is greater than a linear expansion coefficient of the first insulating layer and the second insulating layer, and a melting point of the barrier film is greater than a melting point of the electric fuse.

First claim

We claim:

1 . A semiconductor device, comprising:
a semiconductor substrate; a first interlayer dielectric formed over the semiconductor substrate, the first interlayer dielectric having a trench; an electric fuse comprising:
a main wiring in the trench; and
a barrier film covering a lower face of the main wiring and side faces of the main wiring;
a second interlayer dielectric formed on the first interlayer dielectric such that the second interlayer dielectric directly contacts with the main wiring; and
a first wiring overlapping with the main wiring in a plan view,
wherein the main wiring comprises:
a first portion; and
a second portion connected with the first portion, the second portion having a width greater than a width of the first portion;
wherein the first portion and the second portion are formed in the trench, wherein a linear expansion coefficient of the electric fuse is larger than a linear expansion coefficient of the first interlayer dielectric and the second interlayer dielectric, and wherein a melting point of the main wiring is lower than a melting point of the first interlayer dielectric and the second interlayer dielectric.

2 . The semiconductor device according to the claim 1 , wherein the second portion is formed in the same layer as the first portion.

3 . The semiconductor device according to the claim 1 ,
wherein a linear expansion coefficient of the barrier film is smaller than the linear expansion coefficient of the main wiring, and is larger than the linear expansion coefficient of the first interlayer dielectric and the second interlayer dielectric, and wherein a melting point of the barrier film is higher than the melting point of the main wiring, and is lower than the melting point of the first interlayer dielectric and the second interlayer dielectric.

4 . The semiconductor device according to the claim 1 , wherein the main wiring is comprised of copper film.

5 . The semiconductor device according to the claim 1 ,
wherein the second interlayer dielectric includes first and second layers, wherein the first layer is comprised of Si and O, and wherein the second layer is comprised of Si, C and N.

6 . The semiconductor device according to the claim 1 , wherein the first interlayer dielectric has a dielectric constant of 3 or less.

7 . The semiconductor device according to the claim 1 , wherein the main wiring is surrounded by a plurality of wirings in a cross-sectional view, perpendicular to the first portion of the main wiring.

8 . The semiconductor device according to the claim 1 , wherein the main wiring is surrounded by a plurality of wirings and a plurality of vias in cross-sectional view perpendicular to the first portion of the main wiring.

9 . The semiconductor device according to the claim 1 , wherein the electric fuse extends inside the trench.

10 . The semiconductor device according to the claim 1 ,
wherein the main wiring comprises a third portion connected with the second portion, and wherein the third portion has a width smaller than the width of the second portion.

11 . The semiconductor device according to the claim 10 , wherein a plurality of vias are formed on the third portion.

12 . The semiconductor device according to the claim 9 ,
wherein the main wiring comprises a third portion connected with the second portion, and wherein the third portion has a width smaller than the width of the second portion.

13 . The semiconductor device according to the claim 12 , wherein a plurality of vias are formed on the third portion.

14 . The semiconductor device according to the claim 1 , wherein the main wiring is configured such that the first portion is cut by receiving a supply of an electrical current to the main wiring.

15 . The semiconductor device according to the claim 13 , wherein the main wiring is configured such that the first portion is cut by receiving a supply of an electrical current to the main wiring.

16 . The semiconductor device according to the claim 1 , wherein the main wiring is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit.

17 . The semiconductor device according to the claim 1 , wherein the electric fuse arranged between a power source electrode and a ground electrode.

18 . The semiconductor device according to the claim 17 , wherein a resistor is arranged between the second portion and the power source electrode.

19 . The semiconductor device according to the claim 18 , further comprising:
a transistor; and a decision circuit configured to detect whether or not a resistance of the electric fuse is equal to or greater than a predetermined value, wherein the transistor and the decision circuit are connected between the resistor and the electric fuse.

Assignees

• Renesas Electronics Corp

Inventors

• Iwamoto Takeshi
• Kono Kazushi
• Arakawa Masashi
• Yonezu Toshiaki
• Obayashi Shigeki

Classifications

• H10W42/80 Primary

  protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/49

  Adaptable interconnections, e.g. fuses or antifuses · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title