Method and apparatus for determining feasibility of memory operating condition change using different back bias voltages

Patent metadata

Field	Value
Publication number	US-9817601-B1
Application number	US-201615204190-A
Country	US
Kind code	B1
Filing date	Jul 7, 2016
Priority date	Jul 7, 2016
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A memory device having at least one output predicting a feasibility of whether the memory device will work properly at a different operating condition including a different supply voltage and/or a different operating frequency than the current supply voltage and/or the current operating frequency. A semiconductor device (e.g. a SoC chip) provides a test to either validate or invalidate the feasibility for the memory device to enter such a different operating condition based on read and write operations of the memory device in normal access cycles. The memory device is partitioned with at least a first memory unit and a second memory unit, which can be coupled to different back-bias voltages. This operating condition predicting function can be enabled or disabled by the semiconductor device in real time operation depending on the feasibility test results.

First claim

What is claimed is:

1. A method of operating a memory device, the method comprising:
writing a data into both a first memory unit of the memory device and a second memory unit of the memory device while the memory device is operating at a first operating condition including a first supply voltage being supplied to both the first memory unit and the second memory unit and the memory device is at a first operating frequency;
reading, after the writing, the data from the first memory unit and from the second memory unit while the memory device is operating in the first operating condition, wherein the reading is performed while a first back bias voltage is being provided to transistors of a first conductivity type of the first memory unit and a second back bias voltage is being provided to transistors of the first conductivity type of the second memory unit, the first back bias voltage is different from the second back bias voltage;
comparing the data read from the first memory unit with the data read from the second memory unit;
determining based on the comparing, a feasibility of a second operating condition of the memory device, wherein the second operating condition is different than the first operating condition by at least one of a group consisting of a different supply voltage from the first supply voltage to a memory unit of the memory device and a different operating frequency than the first operating frequency; and
if determined to be feasible, operating the memory device at the second operating condition, wherein operating the memory device includes reading and writing data to the first memory unit in the second operating condition.

2. The method of claim 1 , wherein the writing and reading further comprising:
writing the data into both the first memory unit and the second memory unit of the memory device at a same address for both the first memory unit and the second memory unit; and
reading the data from both the first memory unit and the second memory unit of the memory device at the same address.

3. The method of claim 1 , wherein the first memory unit and the second memory unit are coupled to a same set of wordlines, a same set of sense amplifier control signals and a same set of write control signals.

4. The method of claim 1 , where the determining further comprising:
determining whether the data read from the first memory unit matches the data read from the second memory unit;
incrementing a first count in a first register as a result of a match from the determining;
validating the second operating condition of the memory device if the first count is greater than a first predetermined number;
transitioning from the first operating condition to the second operating condition based on the validating; and
resetting the first count as a result of entering the second operating condition.

5. The method of claim 1 , further comprising:
determining whether the data read from the first memory unit mismatches the data read from the second memory unit;
setting a flag indicating a predictable failure condition of the memory device to transition to the second operating condition as a result of a mismatch found from the determining.

6. The method of claim 1 , further comprising:
wherein operating at the second operating condition includes operating at a lower supply voltage than the first supply voltage.

7. The method of claim 6 , wherein operating at the first operating condition and the second operating condition includes operating at a same operating frequency applied to the memory device.

8. The method of claim 1 , wherein operating at the second operating condition includes operating at a higher operating frequency than the first operating frequency.

9. The method of claim 8 , wherein operating at the first operating condition and the second operating condition includes operating with the first supply voltage applied to the memory device.

10. A semiconductor device comprising:
a first memory unit of a memory device comprising a first back bias terminal for biasing transistors of a first conductivity type,
a second memory unit of the memory device comprising a second back bias terminal for biasing transistors of the first conductivity type;
a data input coupled to write data to the first memory unit and to the second memory unit concurrently;
a back bias generator including a first output to provide a back bias voltage to the first back bias terminal and a second output to provide a back bias voltage to the second back bias terminal, wherein the back bias generator can provide different back bias voltages to the first back bias terminal and the second back bias terminal at a same time;
a control unit including circuitry, the control unit includes:
a first output coupled to the back bias generator to control the back bias voltage provided to the second back bias terminal;
a comparison circuit including a first comparator input, a second comparator input, and a match output, the first comparator input is operably coupled to a data output of the first memory unit, the second comparator input is operably coupled to a data output of the second memory unit, the match output provides a determination of whether data received at the first comparator input and the second comparator input match;
a second output to provide an operating condition parameter value of the memory device from a plurality of operating condition parameter values associated with an operating condition parameter, wherein the operating condition parameter includes one of a group consisting of a supply voltage provided to the memory device, an operating frequency of the memory device, wherein the operating condition parameter value indicated by the second output is dependent upon the match output of the comparison circuit comparing data from the first memory unit and the second memory unit during a read operation where a back bias voltage provided to the first back bias terminal was different than a back bias voltage provided to the second back bias terminal.

11. The semiconductor device of claim 10 , wherein the control unit further comprises:
a first status indicator wherein the first status indicator is set to a first state at power on;
wherein the first status indicator is changed to a second state in response to the match output providing a determination of the data received at the first comparator input and the data received at the second comparator input does not match.

12. The semiconductor device of claim 10 , wherein:
a first operating condition parameter value is indicative of a first operating condition and a second operating condition parameter value is indicating of a second operating condition;
the first operating condition includes a first supply voltage provided to the memory device; and
the second operating condition includes a second supply voltage provided to the memory device different than the first supply voltage.

13. The semiconductor device of claim 10 , wherein:
a first operating condition parameter value is indicative of a first operating condition and a second operating condition parameter value is indicating of a second operating condition;
the first operating condition includes a first operating frequency being provided to the memory device; and
the second operating condition includes a second operating frequency provided to the memory device different than the first operating frequency.

14. The semiconductor device of claim 10 , wherein the control unit further comprising:
a first counter having an input, wherein the input of the first counter is coupled to the match output of the comparison circuit,

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Zhang Shayan
• Mahatme Nihaar
• Pandey Rakesh

Classifications

• G11C11/413

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title

• G11C7/1045

  Read-write mode select circuits · CPC title

• G11C2029/0409

  Online test · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title