Receiving circuit with offset voltage compensation

Patent metadata

Field	Value
Publication number	US-10923074-B2
Application number	US-201916354358-A
Country	US
Kind code	B2
Filing date	Mar 15, 2019
Priority date	Apr 24, 2018
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

A receiving circuit includes a first capacitor connected to a first signal line, a second capacitor connected to a second signal line. A first bias control circuit may convert a common mode voltage of a first received signal provided through the first capacitor to a first voltage level to output a first biased signal. A second bias control circuit may convert a common mode voltage of a second received signal provided through the second capacitor to a second voltage level to output a second biased signal. A balance compensation circuit may receive the first biased signal and the second biased signal, compensate for an offset voltage of the first biased signal based on the second biased signal, and compensate for an offset voltage of the second biased signal based on the first biased signal to output a first differential signal and a second differential signal.

First claim

What is claimed is:

1. A receiving circuit comprising:
a first capacitor connected to a first signal line;
a second capacitor connected to a second signal line;
a first bias control circuit configured to convert a common mode voltage of a first received signal provided through the first capacitor to a first voltage level to output therefrom a first biased signal;
a second bias control circuit configured to convert a common mode voltage of a second received signal provided through the second capacitor to a second voltage level to output therefrom a second biased signal; and
a balance compensation circuit configured to receive the first biased signal and the second biased signal compensate for an offset voltage of the first biased signal based on the second biased signal, and compensate for an offset voltage of the second biased signal based on the first biased signal to output therefrom a first differential signal and a second differential signal.

2. The receiving circuit of claim 1 , wherein the balance compensation circuit comprises:
a first filter circuit for removing a high-frequency component from the first biased signal to output therefrom a first filtered signal;
a second filter circuit for removing a high-frequency component from the second biased signal to output therefrom a second filtered signal; and
an amplifier for receiving the first biased signal and the second filtered signal as a first input signal, receiving the second biased signal and the first filtered signal as a second input signal, and generating therefrom the first differential signal and the second differential signal.

3. The receiving circuit of claim 2 , wherein the amplifier comprises:
a first resistor connected between a source voltage and a second output terminal;
a second resistor connected between the source voltage and a first output terminal;
a first transistor comprising a first electrode connected to the second output terminal, a second electrode connected to a bias node, and a gate electrode receiving the first biased signal;
a second transistor comprising a first electrode connected to the first output terminal, a second electrode connected to the bias node, and a gate electrode receiving the first filtered signal;
a third transistor comprising a first electrode connected to the second output terminal, a second electrode connected to the bias node, and a gate electrode receiving the second filtered signal;
a fourth transistor comprising a first electrode connected to the first output terminal, a second electrode connected to the bias node, and a gate electrode receiving the second biased signal; and
a fifth transistor comprising a first electrode connected to the bias node, a second electrode connected to a reference ground, and a gate electrode receiving a bias signal.

4. The receiving circuit of claim 2 , wherein each of the first filter circuit and the second filter circuit comprises a low pass filter.

5. The receiving circuit of claim 2 , wherein the first filter circuit comprises:
a first filter resistor connected between a first node receiving the first biased signal and a second node; and
a first filter capacitor connected between the second node and a reference ground.

6. The receiving circuit of claim 2 , wherein each of the first filter circuit and the second filter circuit changes an operation characteristic thereof in response to a resistance selection signal and a capacitance selection signal.

7. The receiving circuit of claim 6 , wherein the first filter circuit comprises:
a plurality of filtering resistors having different resistances from each other;
a plurality of capacitors having different capacitances from each other;
a first switching circuit connecting one filtering resistor among the filtering resistors between a first node receiving the first biased signal and a second node in response to the resistance selection signal; and
a second switching circuit connecting one capacitor among the capacitors between the second node and a reference ground in response to the capacitance selection signal.

8. The receiving circuit of claim 1 , wherein the first bias control circuit selects the first voltage level in response to a bias control signal, and the second bias control circuit selects the second voltage level in response to the bias control signal.

9. The receiving circuit of claim 1 , wherein the first voltage level is substantially the same as the second voltage level.

10. The receiving circuit of claim 1 , further comprising a clock and data recovery circuit to recover a clock signal and a data signal based on the first differential signal and the second differential signal.

11. A receiver comprising:
a receiving circuit configured to convert a first received signal and a second received signal to a first differential signal and a second differential signal, respectively;
a clock and data recovery circuit configured to recover a clock signal and a data signal based on the first differential signal and the second differential signal; and
a coupling selection circuit configured to apply a first signal and a second signal provided, respectively, through a first signal line and a second signal line, to the receiving circuit as the first received signal and second received signal, respectively, or to the clock and data recovery circuit as the first differential signal and the second differential signal, respectively, in response to a coupling control signal;
wherein the receiving circuit comprises:
a first capacitor connected to the first signal line through the coupling selection circuit;
a second capacitor connected to the second signal line through the coupling selection circuit;
a first bias control circuit configured to convert a common mode voltage of the first received signal provided through the first capacitor to a first voltage level to output therefrom a first biased signal;
a second bias control circuit configured to convert a common mode voltage of the second received signal provided through the second capacitor to a second voltage level to output therefrom a second biased signal; and
a balance compensation circuit configured to receive the first biased signal and the second biased signal, compensate for an offset voltage of the first biased signal using the second biased signal, and compensate for an offset voltage of the second biased signal using the first biased signal to output therefrom the first differential signal and the second differential signal.

12. The receiver of claim 11 , wherein the coupling selection circuit comprises:
first and second switching elements respectively and selectively connecting the first signal line and the second signal line to the first capacitor and the second capacitor in response to the coupling control signal; and
third and fourth switching elements applying the first signal of the first signal line and the second signal of the second signal line to the clock and data recovery circuit as the first differential signal and the second differential signal in response to the coupling control signal.

13. The receiver of claim 11 , wherein the balance compensation circuit comprises:
a first filter circuit removing a high-frequency component from the first biased signal to output a first filtered signal;
a second filter circuit removing a high-frequency component from the second biased signal to output a second filtered signal; and
an amplifier receiving the first biased signal and the second filtered as a first input signal, receiving the second biased signal and the first filtered signal as a second input signal, and outputting therefrom the first differential sign

Assignees

• Samsung Display Co Ltd

Inventors

• Pyun Kihyun
• Shin Seung-Woon
• Cho Eui-Myeong

Classifications

• G09G3/3688

  suitable for active matrices only · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G3/3275

  Details of drivers for data electrodes · CPC title

• H03F2203/45156

  At least one capacitor being added at the input of a dif amp · CPC title

• G09G2370/14

  Use of low voltage differential signaling [LVDS] for display data communication · CPC title