Dual device semiconductor structures with shared drain

Patent metadata

Field	Value
Publication number	US-10917052-B2
Application number	US-201916376664-A
Country	US
Kind code	B2
Filing date	Apr 5, 2019
Priority date	Mar 16, 2016
Publication date	Feb 9, 2021
Grant date	Feb 9, 2021

Abstract

Transistors may be manufactured with a shared drain to reduce die area consumed by circuitry. In one example, two transistors can be manufactured that include two body regions that abut a shared drain region. The two transistors can be independently operated by coupling terminals to a source and a gate for each transistor and the shared drain. Characteristics of the two transistors can be controlled by adjusting feature sizes, such as overlap between the gate and the shared drain for a transistor. In particular, two transistors with different voltage requirements can be manufactured using a shared drain structure, which can be useful in amplifier circuitry and in particular Class-D amplifiers.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor structure, comprising:
forming a first body for a first channel of a first transistor and a second body for a second channel of a second transistor, wherein the first body and the second body are formed to abut a shared drain, wherein the first body and the second body are isolated by a buried layer from a substrate;
forming a first source and a second source, wherein the first source and the second source are isolated by a buried layer from the substrate: and
forming a first gate and a second gate,
wherein the shared drain is coupled to the buried layer of the substrate such that the first source and the first body are isolated from the second source and the second body,
wherein the first source, the first body, the first gate, and the shared drain operate as a first transistor, and wherein the second source, the second body, the second gate, and the shared drain operate as a second transistor,
wherein the first transistor is configured to operate at a first voltage requirement and the second transistor is configured to operate at a second voltage requirement.

2. The method of claim 1 , wherein a first overlap distance between the shared drain and the first gate is different than a second overlap distance between the shared drain and the second gate.

3. The method of claim 1 , wherein a first distance between the shared drain and the first source is different than a second distance between the shared drain and the second source.

4. The method of claim 1 , further comprising forming an electrical conductor coupling the shared drain with the first gate and the second gate.

5. The method of claim 1 , wherein the step of forming the first source and the second source comprises implanting ions into the substrate to deposit dopants to form the first source and the second source.

6. The method of claim 1 , wherein the step of forming the first body and the second body comprises implanting ions into the substrate to deposit dopants to form the first body and the second body.

7. The method of claim 1 , wherein the step of forming the first gate and the second gate comprises: deposition of a conductive material; and patterning of the conductive material to form the first gate and the second gate.

8. The method of claim 1 , wherein the step of forming the first gate and the second gate comprises deposition of a conductive material in a patterned structure to form the first gate and the second gate.

9. The method of claim 1 , further comprising depositing an insulating layer on the first body and the second body before forming the first gate and the second gate, such that the first gate and the second gate are not formed in direct contact with the first body and the second body.

10. The method of claim 1 , further comprising forming a conductive block coupling the shared drain to the first gate and the second gate.

11. The method of claim 10 , wherein forming the conductive block comprises forming a silicide block.

12. The method of claim 11 , further comprising forming a first terminal on the first source, a second terminal on the first gate, a third terminal on the silicide block, a fourth terminal on the second source, and a fifth terminal on the second gate, wherein the first terminal, the second terminal, and the third terminal comprise three terminals of the first transistor, and wherein the third terminal, the fourth terminal, and the fifth terminal comprise three terminals of the second transistor.

13. The method of claim 1 , further comprising forming a third gate and forming a third source, wherein the shared drain is coupled to the buried layer of a substrate such that the first source and the first body are isolated from the third source and the third body.

14. The method of claim 1 , forming integrated circuitry to abut the shared drain, wherein the integrated circuitry comprises an audio amplifier.

15. The method of claim 4 , wherein forming the electrical conductor comprises forming an electrical conductor configured to allow the shared drain to float during operation of the first transistor.

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Pan Shanjen
• Tarabbia Marc L
• Larsen Christian

Classifications

• H10D89/10

  Integrated device layouts · CPC title

• H10D84/013

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/0133 Primary

  Manufacturing common source or drain regions between multiple IGFETs · CPC title