Semiconductor die for determining load of through silicon via and semiconductor device including the same

Patent metadata

Field	Value
Publication number	US-10916525-B2
Application number	US-201816125975-A
Country	US
Kind code	B2
Filing date	Sep 10, 2018
Priority date	Mar 12, 2018
Publication date	Feb 9, 2021
Grant date	Feb 9, 2021

Abstract

A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.

First claim

What is claimed is:

1. A semiconductor die, comprising:
a first delay circuit on a substrate, the first delay circuit configured to delay a test signal to generate a first delay signal, the first delay circuit including first delay stages connected in series, the first delay stages including output terminals;
a second delay circuit on the substrate, the second delay circuit configured to delay the test signal to generate a second delay signal such that the first delay circuit and the second delay circuit each receive a same one of the test signal, the second delay circuit including second delay stages connected in series, the second delay stages including output terminals;
at least one through silicon via connected to at least one of the output terminals of the first delay stages and disconnected from the output terminals of the second delay stages, the at least one through silicon via penetrating through the substrate; and
processing circuitry configured to determine a load of the at least one through silicon via based on a difference between the first delay signal and the second delay signal.

2. The semiconductor die of claim 1 , wherein
a first propagation delay of one of the first delay stages connected to the at least one of the output terminals is influenced by the at least one through silicon via, and
a second propagation delay of each of the second delay stages is not influenced by the at least one through silicon via.

3. The semiconductor die of claim 2 , wherein
each of the second delay stages includes a same at least one logic gate as corresponding ones of the first delay stages, and
each of the second delay stages is adjacent to the corresponding ones of the first delay stages.

4. The semiconductor die of claim 2 , wherein
a first terminal of the at least one through silicon via is connected to the at least one of the output terminals of the first delay stages, and
a second terminal of the at least one through silicon via is in a floating state.

5. The semiconductor die of claim 1 , wherein the processing circuitry is configured to,
determine a first delay based on the first delay signal and the test signal; and
determine a second delay based on the second delay signal and the test signal.

6. The semiconductor die of claim 1 , further comprising:
an output circuit configured to output, through at least one pad to an outside, first output signals of the first delay stages and second output signals of the second delay stages.

7. The semiconductor die of claim 1 , wherein
the first delay stages are configured to generate a first clock based on the test signal, the first delay stages including an initial first delay stage receiving the test signal and a final first delay stage, an output terminal of the final first delay stage being connected to the initial first delay stage, and a number of first logic gates of the first delay stages is odd,
the second delay stages are configured to generate a second clock based on the test signal, the second delay stages including an initial second delay stage receiving the test signal and a final second delay stage, an output terminal of the final second delay stage being connected to the initial second delay stage, and a number of second logic gates of the second delay stages is odd, and
the processing circuitry is configured to determine the load of the at least one through silicon via based on the first clock with the second clock.

8. The semiconductor die of claim 1 , further comprising:
a first multiplexer configured to select first output signals, which are output from the first delay stages, respectively, and to transmit the first delay signal to the processing circuitry; and
a second multiplexer configured to select second output signals, which are output from the second delay stages, respectively, and to transmit the second delay signal to the processing circuitry.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Woo Seunghan
• Ryu Je Min
• Oh Reum
• Oh Moonhee
• Lee Bumsuk

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/284

  characterised by structural arrangements for measuring or testing · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title