Methods of forming metal silicide layers and metal silicide layers formed therefrom

Patent metadata

Field	Value
Publication number	US-10916433-B2
Application number	US-201916366539-A
Country	US
Kind code	B2
Filing date	Mar 27, 2019
Priority date	Apr 6, 2018
Publication date	Feb 9, 2021
Grant date	Feb 9, 2021

Abstract

Methods for forming low resistivity metal silicide interconnects using one or a combination of a physical vapor deposition (PVD) process and an anneal process are described herein. In one embodiment, a method of forming a plurality of wire interconnects includes flowing a sputtering gas into a processing volume of a processing chamber, applying a power to a target disposed in the processing volume, forming a plasma in a region proximate to the sputtering surface of the target, and depositing the metal and silicon layer on the surface of the substrate. Herein, the first target comprises a metal silicon alloy and a sputtering surface thereof is angled with respect to a surface of the substrate at between about 10° and about 50°.

First claim

The invention claimed is:

1. A method of processing a substrate, comprising:
forming a metal and silicon layer on a surface of the substrate having a plurality of openings formed therein, comprising:
flowing a sputtering gas into a first processing volume, wherein the first processing volume is a processing volume of a first processing chamber;
applying a power to a target disposed in the first processing volume, wherein the target comprises a metal-silicon alloy and a sputtering surface thereof is angled with respect to the surface of the substrate at between about 10° and about 50°;
forming a plasma in a region proximate to the sputtering surface of the target; and
depositing the metal and silicon layer on the surface of the substrate to fill the plurality of openings to at least a level of the surface; and

annealing the metal and silicon layer in a second processing volume, wherein the second processing volume is a processing volume of a second processing chamber, and wherein annealing the metal and silicon layer comprises:
pressurizing the second processing volume to a pressure of more than about 1 times atmospheric pressure using a pressurized gas delivered thereinto;
heating the substrate to an anneal temperature of not more than about 400° C.; and
maintaining the substrate at the anneal temperature for about 30 seconds or more.

2. The method of claim 1 , further comprising:
transferring the substrate from the first processing volume to the second processing volume using a transfer chamber that connects the first processing chamber to the second processing chamber.

3. The method of claim 1 , wherein the metal of the metal-silicon alloy is Ti, Ni, Pt, Co, or a combination thereof.

4. The method of claim 3 , wherein the metal-silicon alloy is an amorphous nickel-silicon alloy having an atomic composition of Ni x Si (1-x) , and wherein X is between about 0.4 and about 0.6.

5. The method of claim 4 , wherein the substrate comprises a dielectric layer having the plurality of openings formed therein, and wherein the annealed metal and silicon layer forms a plurality of NiSi interconnects in the plurality of openings.

6. The method of claim 5 , wherein a diameter of the first target is about 200 mm or less.

7. The method of claim 5 , further comprising depositing a passivation layer on the metal and silicon layer, the passivation layer comprising one of metal oxide, metal nitride, silicon oxide, silicon nitride, or a combination thereof.

8. The method of claim 5 , wherein the plurality of NiSi interconnects have a resistivity of about 200 μohm-cm or less.

9. A method of processing a substrate, comprising:
depositing an amorphous metal-silicon alloy layer on a surface of the substrate, the substrate comprising a dielectric layer having a plurality of openings formed therein, comprising:
flowing a sputtering gas into a first processing volume of a first processing chamber;
applying a power to a target disposed in the first processing volume, wherein the target comprises a metal-silicon alloy
forming a plasma in a region proximate to a sputtering surface of the target; and
depositing the amorphous metal-silicon alloy layer to fill the plurality of openings to at least a level of the surface of the dielectric layer; and

annealing the substrate, comprising:
positioning the substrate in a second processing volume of a second processing chamber,
pressurizing the second processing volume to a pressure between about 1 times and about 10 times atmospheric pressure using a pressurized gas delivered thereinto;
heating the substrate to an anneal temperature of not more than about 400° C.; and
maintaining the substrate at the anneal temperature for about 30 seconds or more.

10. The method of claim 9 , wherein the amorphous metal-silicon alloy has layer an atomic composition of M x Si (1-x) , wherein X is between about 0.4 and about 0.6.

11. The method of claim 9 , wherein annealing the substrate transforms the amorphous metal-silicon alloy layer to a crystalline metal-silicide layer having a substantially uniform stoichiometry.

12. The method of claim 11 , wherein the metal of the metal-silicon alloy layer comprises Ni.

13. The method of claim 11 , wherein the metal of the metal-silicide layer comprises Ti, Ni, Pt, Co, or a combination thereof.

14. The method of claim 9 , further comprising depositing a passivation layer on the amorphous metal-silicon alloy layer, the passivation layer comprising one of metal oxide, metal nitride, silicon oxide, silicon nitride, or a combination thereof.

15. A method of forming nickel-silicide interconnects, comprising:
depositing a nickel and silicon alloy layer on a surface of a substrate, the substrate comprising a dielectric layer having a plurality of openings formed therein, comprising:
flowing a sputtering gas into a first processing volume of a first processing chamber;
applying a power to a target disposed in the first processing volume, wherein the target comprises a metal-silicon alloy
forming a plasma in a region proximate to a sputtering surface of the target; and
depositing the nickel and silicon alloy layer to fill the plurality of openings to at least a level of the surface of the dielectric layer, wherein the nickel and silicon layer comprises an amorphous nickel-silicon alloy having an atomic composition of N x Si (1-x) , and wherein X is between about 0.4 and about 0.6; and

positioning the substrate in a second processing volume of a second processing chamber;
pressurizing the second processing volume to a pressure between about 1 times and about 10 times atmospheric pressure using a pressurized gas delivered thereinto;
heating the substrate to an anneal temperature of not more than about 400° C.; and
maintaining the substrate at the anneal temperature for about 30 seconds or more.

16. The method of claim 15 , wherein annealing the substrate forms a crystalline nickel-silicide layer having a substantially uniform stoichiometry.

Assignees

• Applied Materials Inc

Inventors

• Ren He
• Clemons Maximillian
• Shek Mei-Yee
• Yu Minrui
• Mebarki Bencherki
• Naik Mehul B
• Ying Chentsau
• Nemani Srinivas D

Classifications

• H10P14/414

  of metal-silicide materials · CPC title

• H10P14/44

  Physical vapour deposition [PVD] · CPC title

• H10W20/4451

  Semiconductor materials, e.g. polysilicon · CPC title

• H10W20/056 Primary

  by filling conductive material into holes, grooves or trenches · CPC title

• H10D64/0112 Primary

  using conductive layers comprising silicides · CPC title