Data lines to fluid ejection devices

Patent metadata

Field	Value
Publication number	US-10913265-B2
Application number	US-201716607441-A
Country	US
Kind code	B2
Filing date	Jul 6, 2017
Priority date	Jul 6, 2017
Publication date	Feb 9, 2021
Grant date	Feb 9, 2021

Abstract

In some examples, a system includes a plurality of fluid ejection devices, a fluid ejection controller, and a plurality of data lines shared by the plurality of fluid ejection devices and connected between the fluid ejection controller and the plurality of fluid ejection devices. A first data line of the plurality of data lines communicates data of a first memory of a first fluid ejection device of the plurality of fluid ejection devices, and a second data line of the plurality of data lines communicates data of a second memory of the first fluid ejection device.

First claim

What is claimed is:

1. A system comprising:
a plurality of fluid ejection devices;
a fluid ejection controller; and
a plurality of data lines shared by the plurality of fluid ejection devices and connected between the fluid ejection controller and the plurality of fluid ejection devices,
a first data line of the plurality of data lines to communicate data of a first memory of a first fluid ejection device of the plurality of fluid ejection devices, and
a second data line of the plurality of data lines to communicate data of a second memory of the first fluid ejection device, wherein the first and second data lines are to communicate data of the first and second memories in parallel.

2. The system of claim 1 , wherein the plurality of data lines are ID lines.

3. The system of claim 1 , wherein:
the first data line is to communicate data of a first memory of a second fluid ejection device of the plurality of fluid ejection devices, and
the second data line is to communicate data of a second memory of the second fluid ejection device.

4. The system of claim 3 , wherein the first and second data lines are to communicate data of the first and second memories in the first fluid ejection device that is to eject a first type of fluid, and
wherein the first and second data lines are to communicate data of the first and second memories in the second fluid ejection device that is to eject a second type of fluid different from the first type of fluid.

5. The system of claim 3 , wherein the first fluid ejection device is a first fluid ejection die, and the second fluid ejection device is a second fluid ejection die.

6. The system of claim 1 , further comprising:
first address lines between the fluid ejection controller and the first fluid ejection device, the first address lines to provide addresses to the first and second memories of the first fluid ejection device; and
second address lines between the fluid ejection controller and a second fluid ejection device of the plurality of fluid ejection devices, the second address lines to provide addresses to memories of the second fluid ejection device.

7. The system of claim 1 , further comprising:
a first fire line between the fluid ejection controller and the first fluid ejection device, the first fire line to control activation of a fluid ejection nozzle of the first fluid ejection device; and
a second fire line between the fluid ejection controller and a second fluid ejection device of the plurality of fluid ejection devices, the second fire line to control activation of a fluid ejection nozzle of the second fluid ejection device.

8. The system of claim 1 , comprising:
a plurality of decoders responsive to a common address to activate respective control signals at different times for selecting respective memories of the first fluid ejection device,
each respective decoder of the plurality of decoders comprising a discharge switch to deactivate a control signal of the respective decoder while another decoder of the plurality of decoders is activating a control signal in response to the common address.

9. A system comprising:
a plurality of fluid ejection devices;
a fluid ejection controller;
a plurality of data lines shared by the plurality of fluid ejection devices and connected between the fluid ejection controller and the plurality of fluid ejection devices,
a first data line of the plurality of data lines to communicate data of a first memory of a first fluid ejection device of the plurality of fluid ejection devices, and
a second data line of the plurality of data lines to communicate data of a second memory of the first fluid ejection device;
a plurality of decoders responsive to a common address to activate respective control signals at different times for selecting respective memories of the first fluid ejection device,
each respective decoder of the plurality of decoders comprising a discharge switch to deactivate a control signal of the respective decoder while another decoder of the plurality of decoders is activating a control signal in response to the common address.

10. The system of claim 9 , wherein the respective decoder comprises a first stage, a second stage, and a pass gate, and wherein the first stage is to evaluate the common address in response to activation of a first select signal, and the pass gate is to pass an output of the first stage to the second stage in response to activation of a second select signal that is activated after the first select signal, and the pass gate to isolate a node of the first stage from a node of the second stage so that an address data that is being shifted is not lost due to discharge performed by the discharge switch.

11. The system of claim 10 , wherein the respective decoder comprises a shift register comprising a plurality of shift register cells, and wherein the first stage, the second stage, and the pass gate are part of a shift register cell of the plurality of shift register cells.

12. The system of claim 9 , wherein the first fluid ejection device is a first fluid ejection die, and a second fluid ejection device of the plurality of fluid ejection devices is a second fluid ejection die.

13. A method comprising:
connecting a plurality of data lines to a plurality of fluid ejection devices, the plurality of data lines to communicate, in parallel, data between a fluid ejection controller and a plurality of memories in each fluid ejection device of the plurality of fluid ejection devices;
connecting address lines to a first fluid ejection device of the plurality of fluid ejection devices, the address lines supporting an address space of a first size, wherein use of the plurality of data lines to communicate data of the plurality of memories in parallel effectively increases an available address space to a size greater than the first size, and wherein the plurality of fluid ejection devices are addressed to avoid multiple fluid ejection devices being active concurrently on a data line of the plurality of data lines;
providing a plurality of decoders each comprising shift registers to receive respective address bits, the plurality of decoders responsive to a common address on the address bits to activate respective control signals at different times for selecting respective memories of a fluid ejection device; and
including a discharge switch in a shift register of a first decoder of the plurality of decoders, the discharge switch to deactivate a control signal of the first decoder while another decoder of the plurality of decoders is activating a control signal in response to the common address.

14. The method of claim 13 , wherein each of the plurality of fluid ejection devices is a fluid ejection die.

15. A circuit for a fluid ejection device, comprising:
signal pads to receive address signals; and
a plurality of decoders responsive to a common address of the address signals to activate respective control signals at different times for selecting respective memories of the fluid ejection device,
each respective decoder of the plurality of decoders comprising a discharge switch to deactivate a control signal of the respective decoder while another decoder of the plurality of decoders is activating a control signal in response to the common address.

16. The circuit of claim 15 , wherein the respective decoder comprises a first stage, a second stage, and a pass gate, and wherein the first stage is to evaluate the common address in response to activation of a first select signal, and the pass gate is to pass an output of the first stage to the second stage in response to

Assignees

• Hewlett Packard Development Co

Inventors

• Ng Boon Bing
• Pan Rui
• Sudhakar Mohan Kumar
• Hall Brendan

Classifications

• B41J2/04546

  Multiplexing · CPC title

• B41J2/04573

  Timing; Delays · CPC title

• B41J2/04548

  Details of power line section of control circuit · CPC title

• B41J2/04541 Primary

  Specific driving circuit · CPC title

• B41J2/04586 Primary

  controlling heads of a type not covered by groups B41J2/04575 - B41J2/04585, or of an undefined type · CPC title