Circuit that selects EPROMs individually and in parallel

Patent metadata

Field	Value
Publication number	US-9592664-B2
Application number	US-201114343133-A
Country	US
Kind code	B2
Filing date	Sep 27, 2011
Priority date	Sep 27, 2011
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

An integrated circuit including a first EPROM, a second EPROM, and a circuit. The first EPROM is configured to provide a first state and a second state. The second EPROM is configured to provide a third state and a fourth state. The circuit is configured to select the first EPROM and the second EPROM individually and in parallel with each other.

First claim

The invention claimed is:

1. An integrated circuit, comprising:
an EPROM bit comprising:
a bit address transistor;
a first EPROM connected to the bit address transistor and configured to provide a first state and a second state for the EPROM bit;
a second EPROM connected to the bit address transistor and configured to provide a third state and a fourth state for the EPROM bit; and

a circuit configured to select the first EPROM and the second EPROM individually and in parallel with each other, wherein the circuit is configured to select the first EPROM and the second EPROM in parallel to provide a fifth state and a sixth state for the EPROM bit.

2. The integrated circuit of claim 1 , wherein the first EPROM has a first channel width and the second EPROM has a second channel width that is different than the first channel width.

3. The integrated circuit of claim 1 , wherein the first EPROM is a first type of EPROM and the second EPROM is a second type of EPROM that is different than the first type of EPROM.

4. The integrated circuit of claim 1 , wherein the first state corresponds to a first un-programmed resistance having a first resistance value, the second state corresponds to a first programmed resistance having a second resistance value, the third state corresponds to a second un-programmed resistance having a third resistance value, and the fourth state corresponds to a second programmed resistance having a fourth resistance value, wherein each resistance value of the first resistance value, the second resistance value, the third resistance value, and the fourth resistance value is a different resistance value than each of the other three resistance values.

5. The integrated circuit of claim 1 , wherein the EPROM bit further comprises:
a third EPROM connected to the bit address transistor and configured to provide, for the EPROM bit, a seventh state and an eighth state, and the circuit is further configured to select each of the first EPROM and the second EPROM and the third EPROM individually and in parallel with any one or more of the other EPROMs.

6. The integrated circuit of claim 1 , wherein the circuit is configured to select the first EPROM and the second EPROM in parallel to provide the fifth state for the EPROM bit when the first ERPOM provides the first state and the second EPROM provides the third state, and
the circuit is configured to select the first EPROM and the second EPROM in parallel to provide the sixth state for the EPROM bit when the first EPROM provides the first state and the second EPROM provides the fourth state.

7. The integrated circuit of claim 1 , wherein the circuit is configured to select the first EPROM and the second EPROM in parallel to provide a seventh state and an eighth state for the EPROM bit.

8. The integrated circuit of claim 7 , wherein the EPROM bit further comprises:
a third EPROM connected to the bit address transistor and configured to provide a ninth state and a tenth state for the EPROM bit.

9. The integrated circuit of claim 1 , wherein the circuit is configured to select the first EPROM and the second EPROM in parallel to provide, for the EPROM bit, the fifth state and the sixth state based at least in part on whether the first EPROM is to provide the first state and the second EPROM is to provide the third state.

10. A printhead, comprising:
a first EPROM configured to provide a first un-programmed resistance having a first resistance value and a first programmed resistance having a second resistance value;
a second EPROM configured to provide a second un-programmed resistance having a third resistance value and a second programmed resistance having a fourth resistance value;
a bit address transistor configured to conduct current from each of the first EPROM and the second EPROM, wherein the first resistance value, the second resistance value, the third resistance value, and the fourth resistance value are different resistance values; and
a circuit configured to:
select the first EPROM individually to provide a first state corresponding to the first un-programmed resistance and a second state corresponding to the first programmed resistance for an EPROM bit corresponding to the bit address transistor,
select the second EPROM individually to provide a third state corresponding to the second un-programmed resistance and a fourth state corresponding to the second programmed resistance for the EPROM bit, and
select the first EPROM and the second EPROM in parallel to provide, for the EPROM bit, a fifth state corresponding to the first un-programmed resistance and the second un-programmed resistance, a sixth state corresponding to the first un-programmed resistance and the second programmed resistance, a seventh state corresponding to the first programmed resistance and the second un-programmed resistance, and an eighth state corresponding to the first programmed resistance and the second programmed resistance.

11. The printhead of claim 10 , comprising:
a third EPROM configured to provide a third un-programmed resistance and a third programmed resistance, wherein the bit address transistor is configured to conduct current from each of the first EPROM and the second EPROM and the third EPROM.

12. The printhead of claim 11 , wherein the third un-programmed resistance has a fifth resistance value, the third programmed resistance has a sixth resistance value, and the first resistance value, second resistance value, third resistance value, fourth resistance value, fifth resistance value, and sixth resistance value are different.

13. The printhead of claim 11 , wherein the circuit is configured to select the first EPROM and the second EPROM and the third EPROM individually and in parallel with any one or more of the other EPROMs to measure up to twenty six different resistance values that correspond to up to twenty six states for the EPROM bit.

Assignees

• Ge Ning
• Mikulan Paul I
• Peh Bee Ling
• Hewlett Packard Development Co Lp

Inventors

• Ge Ning
• Mikulan Paul I
• Peh Bee Ling

Classifications

• B41J2/04581

  controlling heads based on piezoelectric elements · CPC title

• G11C11/5621

  using charge storage in a floating gate · CPC title

• G11C16/0458

  comprising two or more independent floating gates which store independent data · CPC title

• H01L27/11521

  Electricity · mapped topic

• H01L29/7881

  Electricity · mapped topic