Interlocking circuit and procedure for blocking a data line

Patent metadata

Field	Value
Publication number	US-10911098-B2
Application number	US-201615758977-A
Country	US
Kind code	B2
Filing date	Sep 12, 2016
Priority date	Sep 18, 2015
Publication date	Feb 2, 2021
Grant date	Feb 2, 2021

Abstract

An interlocking circuit and procedure for suppressing an echo on a receiving line are provided. The interlocking circuit blocks the receiving line when there is a signal on a transmission line. The receiving line has a transmission side at which the echo signal is located and a receiving side at which the echo signal can be blocked. The echo signal of a CAN driver is suppressed such that an actuating component for a headlamp light matrix does not receive any unwanted commands.

First claim

The invention claimed is:

1. An interlocking circuit for suppressing an echo, the circuit comprising:
a receiving line (Rx);
a transmission line (Tx);
wherein the receiving line is locked when there is a signal on the transmission line (Tx),
where the receiving line has a first receiving side at which the echo signal is present as well as a second receiving side at which the echo signal is blocked;
wherein a control signal derived from the signal on the transmission line is on a control line, where the control line is connected to an input of an inverter (INV), which has an output connected to an input of an OR gate for signals with negative logic or an AND gate for signals with positive logic, where a second input of the OR gate or the AND gate is connected to a transmission side of the receiving line and an output of the OR gate or the AND gate to the first receiving side or the second receiving side of the receiving line.

2. The interlocking circuit in accordance with claim 1 , wherein a delay circuit (D 1 +R 1 +C 1 ) influences the control signal (A) such that the interlocking circuit interlocks for a longer period than a period during which the signal is on the transmission line.

3. The interlocking circuit in accordance with claim 2 , wherein the delay circuit connects the transmission line to the control line (A) via a diode and the control line to a supply voltage and a capacitor (C 1 ) to the ground via a resistor (R 1 ).

4. An interlocking circuit for suppressing an echo, the circuit comprising:
a receiving line (Rx);
a transmission line (Tx);
wherein the receiving line is locked when there is a signal on the transmission line (Tx),
where the receiving line has a first receiving side at which the echo signal is present as well as a second receiving side at which the echo signal is blocked;
wherein a CAN driver generates the echo and is connected to the transmission line and the transmission side of the transmission line.

5. An interlocking circuit for suppressing an echo, the circuit comprising:
a receiving line (Rx);
a transmission line (Tx);
wherein the receiving line is locked when there is a signal on the transmission line (Tx),
where the receiving line has a first receiving side at which the echo signal is present as well as a second receiving side at which the echo signal is blocked;
wherein at least one light matrix manager module is connected to the transmission line and the first receiving side or the second receiving side of the receiving line, where a minimum of one light matrix manager module transmits the signal to the transmission line.

6. The interlocking circuit in accordance with claim 5 , wherein the interlocking circuit is positioned on a printed circuit board that also holds a CAN driver, a communication interface and the minimum of one light matrix manager module.

Assignees

• Hella Gmbh & Co Kgaa

Inventors

• Buschmann Peter

Classifications

• H05B47/18

  via data-bus transmission · CPC title

• B60Q1/02

  the devices being primarily intended to illuminate the way ahead or to illuminate other areas of way or environments · CPC title

• H04B3/232 Primary

  using phase shift, phase roll or frequency offset correction · CPC title

• H04L2012/40215

  Controller Area Network CAN · CPC title

• H04L12/40 Primary

  Bus networks · CPC title