Shielded semiconductor package with open terminal and methods of making

US10910322B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10910322-B2
Application numberUS-201816220934-A
CountryUS
Kind codeB2
Filing dateDec 14, 2018
Priority dateDec 14, 2018
Publication dateFeb 2, 2021
Grant dateFeb 2, 2021

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device has a substrate. An electrical component is disposed over a surface of the substrate. An encapsulant is deposited over the electrical component and substrate. A portion of the surface of the substrate remains exposed from the encapsulant. A shielding layer is formed over the encapsulant. A portion of the shielding layer is removed to expose the portion of the surface of the substrate.

First claim

Opening claim text (preview).

What is claimed: 1. A method of making a semiconductor device, comprising: providing a substrate; disposing an electrical component over a surface of the substrate; depositing an encapsulant over the electrical component and substrate, wherein a portion of the surface of the substrate remains exposed from the encapsulant; forming a shielding layer over the encapsulant; and removing a portion of the shielding layer to expose the portion of the surface of the substrate. 2. The method of claim 1 , further including removing the portion of the shielding layer using laser ablation. 3. The method of claim 1 , further including: disposing a mask over the portion of the surface of the substrate; and removing the portion of the shielding layer by removing the mask. 4. The method of claim 1 , further including disposing the substrate over a jig with a tab of the jig over the portion of the surface of the substrate. 5. The method of claim 4 , further including disposing an insulating layer on the tab of the jig and disposing the portion of the surface of the substrate on the insulating layer. 6. The method of claim 1 , wherein the portion of the surface of the substrate includes a terminal or socket. 7. A method of making a semiconductor device, comprising: providing a substrate; disposing an electrical component over a surface of the substrate; depositing an encapsulant over the electrical component and substrate, wherein a portion of the surface of the substrate remains exposed from the encapsulant; disposing the substrate over a jig with a tab of the jig over the portion of the surface of the substrate; forming a shielding layer over the encapsulant while the tab of the jig remains over the portion of the surface of the substrate; and removing the jig to expose the portion of the surface of the substrate. 8. The method of claim 7 , further including: disposing an insulating layer on the tab of the jig; and disposing the portion of the surface of the substrate in physical contact with the insulating layer. 9. The method of claim 8 , wherein the insulating layer covers an entire surface of the jig. 10. The method of claim 8 , wherein the insulating layer is a polyimide layer. 11. The method of claim 7 , wherein the portion of the surface of the substrate includes a terminal or socket. 12. The method of claim 7 , wherein the portion of the surface of the substrate includes a contact pad. 13. A method of making a semiconductor device, comprising: providing a substrate; disposing an electrical component over the substrate; depositing an encapsulant over the electrical component and substrate, wherein a portion of the substrate remains exposed from the encapsulant; forming a shielding layer over the encapsulant; and removing a portion of the shielding layer to expose the portion of the substrate. 14. The method of claim 13 , further including removing the portion of the shielding layer using laser ablation. 15. The method of claim 13 , further including: disposing a mask over the portion of the substrate; and removing the portion of the shielding layer by removing the mask. 16. The method of claim 13 , further including disposing the substrate over a jig with a tab of the jig over the portion of the substrate. 17. The method of claim 16 , further including: disposing an insulating layer on the tab of the jig; and disposing the portion of the substrate on the insulating layer. 18. The method of claim 13 , wherein the portion of the substrate includes a terminal or socket. 19. The method of claim 13 , wherein the portion of the substrate includes a contact pad.

Assignees

Inventors

Classifications

  • using masks for insulating materials · CPC title

  • the substrate having spherical bumps for external connection · CPC title

  • using moulds · CPC title

  • on active surfaces of flip-chip devices, e.g. underfills · CPC title

  • of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills · CPC title

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Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10910322B2 cover?
A semiconductor device has a substrate. An electrical component is disposed over a surface of the substrate. An encapsulant is deposited over the electrical component and substrate. A portion of the surface of the substrate remains exposed from the encapsulant. A shielding layer is formed over the encapsulant. A portion of the shielding layer is removed to expose the portion of the surface of t…
Who is the assignee on this patent?
Stats Chippac Pte Ltd
What technology area does this patent fall under?
Primary CPC classification H10W42/20. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 02 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).