Conductive coating for a microelectronics package

Patent metadata

Field	Value
Publication number	US-10910314-B2
Application number	US-201916712091-A
Country	US
Kind code	B2
Filing date	Dec 12, 2019
Priority date	Dec 21, 2016
Publication date	Feb 2, 2021
Grant date	Feb 2, 2021

Abstract

Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.

First claim

The invention claimed is:

1. A bridge comprising:
a first reference plane;
a second reference plane parallel the first reference plane;
a signal routing layer therebetween, the signal routing layer comprising a plurality of signal routing traces;
a first dielectric layer adjacent the signal routing layer, the first reference plane, and the second reference plane; and
a conductive layer on a side surface of the dielectric layer, wherein the conductive layer electrically couples the first and second reference planes.

2. The bridge of claim 1 , wherein the bridge comprises silicon.

3. The bridge of claim 1 , further comprising a second dielectric layer located adjacent the signal routing layer opposite the first dielectric layer such that the second dielectric layer is located in between the signal routing layer and the first reference plane.

4. A microelectronics device comprising:
a first semiconductor die;
a second semiconductor die; and
a bridge therebetween, the bridge comprising:
a first reference plane;
a second reference plane;
a signal routing layer therebetween;
a dielectric layer adjacent the signal routing layer, the first reference plane, and the second reference plane; and
a conductive layer on a side surface of the dielectric layer, wherein the conductive layer electrically couples the first and second reference planes,

wherein the first semiconductor die is coupled to the second semiconductor die through the bridge.

5. The microelectronics device of claim 4 , further comprising a package substrate.

6. The microelectronics device of claim 5 , wherein the bridge is embedded in the package substrate.

7. The microelectronics device of claim 5 , wherein the first and second semiconductor dies are coupled to the package substrate.

8. The microelectronics device of claim 5 , wherein the package substrate comprises an organic material.

9. The microelectronics device of claim 4 , wherein the bridge comprises silicon.

10. The microelectronics device of claim 4 , wherein the bridge comprises an embedded multi-die interconnect bridge.

11. The microelectronics device of claim 4 , wherein the conductive layer has a thickness of about 4 microns to about 50 microns.

12. The microelectronics device of claim 4 , wherein at least one of the first and second semiconductor dies is in electrical communication with the conductive layer.

13. The microelectronics device of claim 4 , wherein the signal routing layer further comprises a plurality of signal routing traces.

14. The microelectronics device of claim 13 , wherein the conductive layer is configured to provide electromagnetic interference shielding between the plurality of signal routing traces and a radio antenna located proximate the microelectronics device.

15. The microelectronics device of claim 4 , wherein the conductive layer includes a grid of conductive material.

16. The microelectronics device of claim 4 , wherein the conductive layer includes an epoxy filled with a conductive material.

17. The microelectronics device of claim 16 , wherein the conductive material is selected from the group consisting of a polymer, copper, stainless steel, nickel, titanium, silver, gold, iron, aluminum, cobalt, chromium, molybdenum, palladium, platinum, tantalum, tungsten, or any alloy thereof.

18. A microelectronics device comprising:
a first semiconductor die;
a second semiconductor die; and
a bridge therebetween, the bridge comprising:
a reference plane;
a signal routing layer including a plurality of signal routing traces;
a dielectric layer located adjacent to the signal routing layer; and
a conductive layer applied to a vertical surface formed by an edge of each of the reference plane, the signal routing layer, and the dielectric layer, the conductive layer in electrical communication with the reference plane,

wherein the first semiconductor die is coupled to the second semiconductor die through the bridge.

19. The microelectronics device of claim 18 , further comprising a dielectric layer located adjacent the signal routing layer opposite the dielectric layer such that the dielectric layer is located in between the signal routing layer and the reference plane, the conductive layer extending to an edge of the dielectric layer.

20. The microelectronics device of claim 18 , wherein the conductive layer is configured to provide electromagnetic interference shielding between the plurality of signal routing traces and a radio antenna located proximate the microelectronics package.

Assignees

• Intel Corp

Inventors

• Weng Li-Sheng
• Chen Chung-Hao Joseph
• Davies-Venn Emile
• Aygun Kemal
• Modi Mitul B

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W44/248

  for antennas · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title