Conductive coating for a microelectronics package

Patent metadata

Field	Value
Publication number	US-10510667-B2
Application number	US-201615386737-A
Country	US
Kind code	B2
Filing date	Dec 21, 2016
Priority date	Dec 21, 2016
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.

First claim

The invention claimed is:

1. A microelectronics package comprising:
a first reference plane and a second reference plane;
a signal routing layer located in between the first and second reference planes, the signal routing layer including a plurality of signal routing traces;
a first dielectric layer located adjacent to the signal routing layer and the first and second reference planes; and
a conductive layer applied to a side surface of the first dielectric layer such that the conductive layer spans the side surface of the first dielectric layer and electrically couples the first and second reference planes.

2. The microelectronics package of claim 1 , further comprising a second dielectric layer located adjacent the signal routing layer opposite the first dielectric layer such that the second dielectric layer is located in between the signal routing layer and the first reference plane.

3. The microelectronics package of claim 1 ; wherein the conductive layer has a thickness of about 5 microns.

4. The microelectronics package of claim 1 , wherein the conductive layer has a thickness of about 5 microns to about 50 microns.

5. The microelectronics package of claim 1 , wherein the conductive layer has a thickness greater than 50 microns.

6. The microelectronics package of claim 1 , further comprising at least one die located adjacent to and in electrical communication with the conductive layer.

7. The microelectronics package of claim 1 , wherein the conductive layer is configured to provide electromagnetic interference shielding between the plurality of signal routing traces and a radio antenna located proximate the microelectronics package.

8. The microelectronics package of claim 1 , wherein the conductive layer includes a grid of conductive material.

9. The microelectronics package of claim 1 , wherein the conductive layer includes an epoxy filled with a conductive material.

10. The microelectronics package of claim 9 , wherein the conductive material is selected from the group consisting of a polymer, copper, stainless steel, nickel, titanium, silver, gold, iron, aluminum, cobalt, chromium, molybdenum, palladium, platinum, tantalum, tungsten, or any alloy thereof.

11. A microelectronics package comprising:
a reference plane;
a signal routing layer including a plurality of signal routing traces;
a first dielectric layer located adjacent to the signal routing layer; and
a conductive layer applied to a vertical surface formed by an edge of each of the reference plane, the signal routing layer, and the first dielectric layer, the conductive layer in electrical communication with the reference plane.

12. The microelectronics package of claim 11 , further comprising a second dielectric layer located adjacent the signal routing layer opposite the first dielectric layer such that the second dielectric layer is located in between the signal routing layer and the reference plane, the conductive layer extending to an edge of the second dielectric layer.

13. The microelectronics package of claim 11 , wherein the conductive layer is configured to provide electromagnetic interference shielding between the plurality of signal routing traces and a radio antenna located proximate the microelectronics package.

14. The microelectronics package of claim 11 , wherein the conductive layer includes an epoxy filled with a conductive material.

15. The microelectronics package of claim 14 , wherein the conductive material is selected from the group consisting of a polymer, copper, stainless steel, nickel, titanium, silver, gold, iron, aluminum, cobalt, chromium, molybdenum, palladium, platinum, tantalum, tungsten, or any alloy thereof.

16. The microelectronics package of claim 11 , wherein the conductive layer has a thickness of about 5 microns.

17. The microelectronics package of claim 11 , wherein the conductive layer has a thickness of about 5 microns to about 50 microns.

18. The microelectronics package of claim 11 , wherein the conductive layer has a thickness greater than 50 microns.

19. The microelectronics package of claim 11 , further comprising at least one die located adjacent to and in electrical communication with the conductive layer.

20. The microelectronics package of claim 11 , wherein the conductive layer includes a grid of conductive material.

Assignees

• Intel Corp

Inventors

• Weng Li-Sheng
• Chen Chung-Hao Joseph
• Davies-Venn Emile
• Aygun Kemal
• Modi Mitul B

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W44/248

  for antennas · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title