Techniques for representing and processing geometry within an expanded graphics processing pipeline

US10909739B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10909739-B2
Application numberUS-201815881566-A
CountryUS
Kind codeB2
Filing dateJan 26, 2018
Priority dateJan 26, 2018
Publication dateFeb 2, 2021
Grant dateFeb 2, 2021

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  2. Abstract

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  5. First independent claim

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Abstract

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In various embodiments, a parallel processor implements a graphics processing pipeline that generates rendered images. In operation, the parallel processor causes execution threads to execute a task shading program on an input mesh to generate a task shader output specifying a mesh shader count. The parallel processor then generates mesh shader identifiers, where the total number of the mesh shader identifiers equals the mesh shader count. For each mesh shader identifier, the parallel processor invokes a mesh shader based on the mesh shader identifier and the task shader output to generate geometry associated with the mesh shader identifier. Subsequently, the parallel processor performs operations on the geometries associated with the mesh shader identifiers to generate a rendered image. Advantageously, unlike conventional graphics processing pipelines, the performance of the graphics processing pipeline is not limited by a primitive distributor.

First claim

Opening claim text (preview).

What is claimed is: 1. A computer-implemented method for processing image data, the method comprising: causing a first plurality of execution threads to execute a task shading program on an input mesh to generate first task shader output specifying a first mesh shader count, wherein the first mesh shader count specifies a total number of mesh shaders to invoke, and wherein each invoked mesh shader executes a group of threads; receiving the first mesh shader count specified in the first task shader output; and in response to receiving the first mesh shader count specifying the total number of mesh shaders to invoke: generating a first plurality of mesh shader identifiers based on the received first mesh shader count, wherein a total number of mesh shader identifiers included in the first plurality of mesh shader identifiers equals the first mesh shader count, for each mesh shader identifier included in the first plurality of mesh shader identifiers, invoking a mesh shader based on the mesh shader identifier and the first task shader output to generate geometry associated with the mesh shader identifier, and performing one or more operations on the geometries associated with the first plurality of mesh shader identifiers to generate a first rendered image. 2. The computer-implemented method of claim 1 , wherein the task shading program specifies one or more tessellation operations to execute on the input mesh. 3. The computer-implemented method of claim 1 , wherein causing the first plurality of execution threads to execute the task shading program comprises providing a first task identifier associated with a first portion of the input mesh as an input to the task shading program. 4. The computer-implemented method of claim 3 , wherein, when the first task identifier is input into the task shading program, the first plurality of execution threads determines a first level of detail (LOD) based on the first task identifier and computes the first mesh shader count based on the first LOD. 5. The computer-implemented method of claim 1 , wherein causing the first plurality of execution threads to execute the task shading program comprises: generating an application data buffer based on the input mesh; storing the application data buffer in a first memory; and storing the first mesh shader count and an address associated with the application data buffer in an on-chip memory as at least a portion of the first task shader output. 6. The computer-implemented method of claim 5 , further comprising setting a reference count included in the application data buffer equal to the first mesh shader count. 7. The computer-implemented method of claim 6 , wherein invoking the mesh shader based on the mesh shader identifier and the first task shader comprises: reading the address associated with the application data buffer from the on-chip memory; accessing data included in the application data buffer based on the address associated with the application data buffer and the mesh shader identifier to generate the geometry associated with the mesh shader identifier; and decrementing the reference count that is stored in the application data buffer. 8. The computer-implemented method of claim 1 , wherein, when executing the task shading program, the first plurality of execution threads performs one or more transformation operations on a first plurality of vertices included in the input mesh, and the number of execution threads included in the first plurality of execution threads is not equal to the number of vertices included in the first plurality of vertices. 9. The computer-implemented method of claim 1 , wherein invoking the mesh shader based on the mesh shader identifier and the first task shader output comprises: modifying the first task shader output to generate a mesh shader input that specifies the mesh shader identifier; storing the mesh shader input in an on-chip memory; and subsequently causing a second plurality of execution threads to execute a mesh shading program based on the mesh shader input and generate the geometry associated with the mesh shader identifier. 10. The computer-implemented method of claim 9 , wherein, when executing the mesh shading program, the second plurality of execution threads performs one or more transformation operations on a first plurality of graphics primitive included in the input mesh, and the number of execution threads included in the second plurality of execution threads is not equal to the number of graphics primitives included in the first plurality of graphics primitives. 11. A system comprising: an off-chip memory storing a task shading program; and a parallel processor that: causes a first plurality of execution threads to execute the task shading program on an input mesh to generate first task shader output specifying a first mesh shader count, wherein the first mesh shader count specifies a total number of mesh shaders to invoke, and wherein each invoked mesh shader executes a group of threads; receives the first mesh shader count specified in the first task shader output; and in response to receiving the first mesh shader count specifying the total number of mesh shaders to invoke: generates a first plurality of mesh shader identifiers based on the received first mesh shader count, wherein a total number of mesh shader identifiers included in the first plurality of mesh shader identifiers equals the first mesh shader count, for each mesh shader identifier included in the first plurality of mesh shader identifiers, invokes a mesh shader based on the mesh shader identifier and the first task shader output to generate geometry associated with the mesh shader identifier, wherein the geometry is stored in an on-chip memory, and performs one or more operations on the geometries associated with the first plurality of mesh shader identifiers to generate a first rendered image. 12. The system of claim 11 , wherein the task shading program specifies one or more tessellation operations to execute on the input mesh. 13. The system of claim 11 , wherein causing the first plurality of execution threads to execute the task shading program comprises providing a first task identifier associated with a first portion of the input mesh as an input to the task shading program. 14. The system of claim 11 , wherein the processor causes the first plurality of execution threads to execute the task shading program by: generating an application data buffer based on the input mesh; storing the application data buffer in the off-chip memory; and storing the first mesh shader count and an address associated with the application data buffer in the on-chip memory as at least a portion of the first task shader output. 15. The system of claim 14 , wherein the processor sets a reference count included in the application data buffer equal to the first mesh shader count. 16. The system of claim 15 , wherein the processor invokes the mesh shader based on the mesh shader identifier and the first task shader by: reading the address associated with the application data buffer from the on-chip memory; accessing data included in the application data buffer based on the address associated with the application data buffer and the mesh shader identifier to generate the geometry associated with the mesh shader identifier; and decrementing the reference count that is stored in the application data buffer. 17. The system of claim 11 , wherein, when executing the task shading program, the first plurality of execution threads performs one or more transformati

Assignees

Inventors

Classifications

  • Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

  • G06T15/005Primary

    General purpose rendering architectures · CPC title

  • Constructive solid geometry [CSG] using solid primitives, e.g. cylinders, cubes · CPC title

  • Finite element generation, e.g. wire-frame surface description, {tesselation} · CPC title

  • Shading · CPC title

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What does patent US10909739B2 cover?
In various embodiments, a parallel processor implements a graphics processing pipeline that generates rendered images. In operation, the parallel processor causes execution threads to execute a task shading program on an input mesh to generate a task shader output specifying a mesh shader count. The parallel processor then generates mesh shader identifiers, where the total number of the mesh sh…
Who is the assignee on this patent?
Nvidia Corp
What technology area does this patent fall under?
Primary CPC classification G06T15/005. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 02 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 10 related publications on this page (citations in our corpus or others sharing the same primary CPC).