Load balancing and merging of tessellation thread workloads

Patent metadata

Field	Value
Publication number	US-8982124-B2
Application number	US-201213631865-A
Country	US
Kind code	B2
Filing date	Sep 29, 2012
Priority date	Sep 29, 2012
Publication date	Mar 17, 2015
Grant date	Mar 17, 2015

Abstract

In one embodiment described herein, a graphics engine with shader unit thread load balancing functionality executes shader instructions from multiple execution threads in a smaller number of execution threads by combining instructions from multiple threads at runtime. In one embodiment, multiple shader unit threads containing less than a minimum number of instructions are combined to minimize the discrepancy between the shortest and longest thread. In one embodiment, threads are merged when they contain a common output register.

First claim

What is claimed is:

1. A machine implemented method comprising:
analyzing a set of shader execution threads from the shader unit of a graphics pipeline to find a subset of threads that include logic operations on the same output register;
merging the subset of threads that include logic operations that write to a common output register;
combining shader unit instructions from multiple threads in a set of threads into a combined shader unit thread;
dispatching the set of shad…

Assignees

• Li Yunjiu
• Green Michael
• Intel Corp

Inventors

• Li Yunjiu
• Green Michael

Classifications

• G06T15/60

  Physics · mapped topic

• G06T2200/28

  Physics · mapped topic

• G06T1/20 Primary

  Physics · mapped topic

• G06T2210/52

  Physics · mapped topic

• G06T17/20 Primary

  Physics · mapped topic