Digital correlated double sampling circuits and image sensors including the same

Patent metadata

Field	Value
Publication number	US-10904466-B2
Application number	US-201816038806-A
Country	US
Kind code	B2
Filing date	Jul 18, 2018
Priority date	Sep 25, 2017
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

A digital correlated double sampling (CDS) circuit includes a first latch circuit, a first converting circuit, a second converting circuit, a second latch circuit, and a calculating circuit. The first latch circuit latches an input phase shift code based on a first control signal to store first and second phase shift codes. The first converting circuit converts the first and second phase shift codes into first and second Gray codes. The second converting circuit converts the first Gray code and the second Gray code into a first binary code and a second binary code. The second latch circuit latches an output of the second converting circuit based on a second control signal to store the first binary code. The calculating circuit operates on the first binary code and the second binary code to generate a third binary code, and outputs the third binary code.

First claim

What is claimed is:

1. A digital correlated double sampling (CDS) circuit comprising:
a first latch circuit configured to latch an input phase shift code based on a first control signal to sequentially store a first phase shift code and a second phase shift code, the first phase shift code representing a reset component, the second phase shift code representing an image component;
a first converting circuit configured to convert the first phase shift code representing the reset component into a first Gray code and the second phase shift code representing the image component into a second Gray code;
a second converting circuit configured to convert the first Gray code and the second Gray code into a first binary code and a second binary code, respectively;
a second latch circuit configured to latch an output of the second converting circuit based on a second control signal to store the first binary code; and
a calculating circuit configured to subtract the reset component from the image component based on the first binary code and the second binary code to generate a third binary code, and to sequentially output the third binary code, the third binary code representing an effective image component,
wherein the input phase shift code comprises a plurality of phase shift signals having a same period, and
wherein at least one bit of the first Gray code is generated based on at least two of the plurality of phase shift signals.

2. The digital CDS circuit of claim 1 ,
wherein a respective phase of each of the plurality of phase shift signals partially overlaps phases of others of the plurality of phase shift signals,
wherein a least significant bit (LSB) of the first Gray code and an LSB of the second Gray code are generated based on the at least two of the plurality of phase shift signals, and
wherein a most significant bit (MSB) of the first Gray code and an MSB of the second Gray code are generated based on one of the plurality of phase shift signals.

3. The digital CDS circuit of claim 2 , wherein the plurality of phase shift signals comprises a first phase shift signal, a second phase shift signal, and a third phase shift signal,
wherein the first converting circuit comprises:
a first signal line configured to output a first phase shift bit corresponding to the first phase shift signal as a first Gray bit corresponding to the MSB of the first Gray code and/or the second Gray code; and
a first XOR gate configured to perform an XOR operation on a second phase shift bit corresponding to the second phase shift signal and a third phase shift bit corresponding to the third phase shift signal to generate a second Gray bit of the first Gray code and/or the second Gray code.

4. The digital CDS circuit of claim 3 , wherein the second converting circuit includes:
a second XOR gate configured to perform an XOR operation on the first Gray bit and a sign determination bit to generate a first binary bit; and
a third XOR gate configured to perform an XOR operation on the second Gray bit and the first binary bit to generate a second binary bit.

5. The digital CDS circuit of claim 4 , wherein the first signal line outputs a first reset Gray bit corresponding to the MSB of the first Gray code during a first duration for detecting the reset component,
wherein the first XOR gate generates a second reset Gray bit of the first Gray code during the first duration,
wherein the second XOR gate generates a first reset binary bit of the first binary code during the first duration, and
wherein the third XOR gate generates a second reset binary bit of the first binary code during the first duration.

6. The digital CDS circuit of claim 5 , wherein the first signal line outputs a first image Gray bit corresponding to the MSB of the second Gray code during a second duration for detecting the image component,
wherein the first XOR gate generates a second image Gray bit of the second Gray code during the second duration,
wherein the second XOR gate generates a first image binary bit of the second binary code during the second duration, and
wherein the third XOR gate generates a second image binary bit of the second binary code during the second duration.

7. The digital CDS circuit of claim 6 , wherein the sign determination bit has a logic high level during the first duration,
wherein the sign determination bit has a logic low level during the second duration.

8. The digital CDS circuit of claim 4 , wherein the second latch circuit includes:
a first reset latch configured to latch an output of the second XOR gate in response to the second control signal; and
a second reset latch configured to latch an output of the third XOR gate in response to the second control signal.

9. The digital CDS circuit of claim 3 , wherein the first latch circuit includes:
a first image latch configured to latch the first phase shift signal in response to the first control signal;
a second image latch configured to latch the second phase shift signal in response to the first control signal; and
a third image latch configured to latch the third phase shift signal in response to the first control signal.

10. The digital CDS circuit of claim 2 , wherein the plurality of phase shift signals comprises first through (2 n −1)-th phase shift signals each of which has a first period, where n is a natural number greater than or equal to two, and
wherein a phase difference between two phase shift signals among the first through (2 n −1)-th phase shift signals is substantially equal to 1/(2*n) of the first period.

11. The digital CDS circuit of claim 1 , wherein the first binary code corresponds to a negative representation of the first Gray code, and
wherein the calculating circuit comprises:
a 1-bit full adder configured to add the second binary code to the first binary code to generate the third binary code.

12. The digital CDS circuit of claim 11 , further comprising:
a first switch circuit configured to sequentially provide the first binary code stored in the second latch circuit to the 1-bit full adder; and
a second switch circuit configured to sequentially provide the second binary code output from the second converting circuit to the 1-bit full adder.

13. An image sensor comprising:
a pixel array configured to generate a plurality of analog pixel signals based on incident light;
a comparison block configured to compare the plurality of analog pixel signals with a ramp signal to generate a plurality of first control signals and a plurality of second control signals; and
a digital correlated double sampling (CDS) block including a plurality of digital CDS circuits, the digital CDS block configured to perform a digital CDS based on the plurality of first control signals, the plurality of second control signals, and an input phase shift code to generate a plurality of effective image binary codes,
wherein each of the plurality of digital CDS circuits comprises:
a first latch circuit configured to latch the input phase shift code based on one of the plurality of first control signals to sequentially store a first phase shift code and a second phase shift code, the first phase shift code representing a reset component, the second phase shift code representing an image component;
a first converting circuit configured to convert the first phase shift code representing the reset component into a first Gray code and the second phase shift code representing the image component into a second Gray code;
a second converting circuit configured to convert the first Gray code and the second Gray code into a first binary code and a second binary code, respectively;
a second latc

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Hyeok-Jong

Classifications

• H04N25/65

  applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS · CPC title

• H04N25/616 Primary

  involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H03M1/123

  Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title