Analog-to-digital converter configured to operate at high speed and image sensor including the same

Patent metadata

Field	Value
Publication number	US-9681082-B2
Application number	US-201414521821-A
Country	US
Kind code	B2
Filing date	Oct 23, 2014
Priority date	Dec 24, 2013
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

Provided is an image sensor including a pixel array including a plurality of pixels and an analog-to-digital converter (ADC) configured to compare a reference voltage with an analog voltage output by the pixel array and latch and decode a comparison result. The ADC is controlled in response to clock information and a counter clock, which are obtained by expanding and encoding a master clock.

First claim

What is claimed is:

1. An image sensor comprising:
a pixel array including a plurality of pixels; and
an analog-to-digital converter (ADC) configured to receive a master clock, the ADC including,
comparators configured to generate comparison results by comparing a reference voltage with a respective one of a plurality of analog voltages output by the pixel array,
latches configured to latch the comparison results in response to encoded clock information and a counter clock, and
a control signal generator configured to generate the encoded clock information and the counter clock by expanding and encoding the master clock, the control signal generator including,
a first latch controller configured to expand the master clock, generate a multi-phase clock, and provide the encoded clock information to at least one first latch of the latches as a first latch control signal, and
a second latch controller configured to provide a second latch control signal to at least one second latch of the latches, the second latch control signal sequentially increasing in response to the master clock.

2. The image sensor of claim 1 , wherein the first latch controller comprises:
a delay locked loop (DLL) circuit configured to generate a multi-phase clock having a phase difference in response to the master clock;
a pulse generator configured to generate pulse signals corresponding to the generated multi-phase clock; and
a pulse combiner configured to combine the pulse signals to generate the first latch control signal.

3. The image sensor of claim 2 , wherein the pulse combiner comprises:
one of a gray code converter, an encoder, and a multiplexer.

4. The image sensor of claim 1 , wherein the first latch controller comprises:
a multi-phase phase locked loop (PLL) circuit configured to generate a multi-phase clock having a phase difference in response to the master clock;
a pulse generator configured to generate pulse signals corresponding to the generated multi-phase clock; and
a pulse combiner configured to combine the pulse signals to generate the first latch control signal.

5. The image sensor of claim 4 , wherein the pulse combiner comprises:
one of a gray code converter, an encoder, and a multiplexer.

6. The image sensor of claim 1 , wherein the second latch controller comprises:
a gray counter configured to generate a gray code and provide the gray code to at least one of the latches as the second latch control signal.

7. An image sensor comprising:
a pixel array including a plurality of pixels configured to output an analog voltages;
a ramp voltage generator configured to generate a ramp voltage;
latches configured to latch in response to a code signal to store comparison results; and
an analog-to-digital converter (ADC) including,
comparators configured to compare the ramp voltage with a respective one of the analog voltages and output the comparison results,
a control signal generator configured to generate the code signal independent of a counter and a counter clock generated using the counter, the control signal generator including,
a first latch controller configured to expand the master clock, generate a multi-phase clock, and provide the code signal to at least one first latch of the latches as a first latch control signal, and
a second latch controller configured to provide the counter clock serving as a second latch control signal to at least one second latch of the latches, the second latch control signal sequentially increasing in response to the master clock.

8. The image sensor of claim 7 , wherein the first latch controller comprises:
a multi-phase clock generating circuit configured to generate a multi-phase clock having a phase difference in response to the master clock;
a pulse generator configured to generate pulse signals corresponding to the generated multi-phase clock; and
a pulse combiner configured to combine the pulse signals to generate the first latch control signal.

9. The image sensor of claim 8 , wherein the multi-phase clock generating circuit comprises:
one of a delay locked loop (DLL) circuit and a multi-phase phase locked loop (PLL) circuit.

10. The image sensor of claim 8 , wherein the pulse combiner comprises:
one of a gray code converter, an encoder, and a multiplexer.

11. The image sensor of claim 7 , wherein the second latch controller comprises:
a gray counter configured to generate a gray code and provide the gray code to at least one of the latches as the second latch control signal.

12. An analog-to-digital converter (ADC) configured to convert analog pixel signals from a pixel array to a digital signal, the ADC converter comprising:
a control signal generator configured to generate a plurality of encoded pulse signals based on an external master clock signal such that the plurality of encoded pulse signals have an increased number of phases and fewer bits than the external master clock signal, the control signal generator including,
a first latch controller configured to generate a first gray code by combining the plurality of encoded pulse signals, and
a second latch controller configured to generate a second gray code that sequentially increases based on pulses of the external master clock signal;

comparators configured to generate comparison signals each indicating which of a reference voltage and a voltage of a respective one of the analog pixel signals is larger; and
latches each configured to store a respective one of the comparison signals in response to one of the first gray code and the second gray code.

13. The ADC converter of claim 12 , wherein the external master clock signal is a phase-locked loop clock signal and the control signal generator is configured to generate the plurality of encoded pulse signals without using a column counter in columns of the pixel array.

14. The ADC converter of claim 12 , wherein the latches include,
first latches configured to store least significant bits (LSBs) of the comparison signals in response to the first gray code; and
second latches configured to store most significant bits (MSBs) of the comparison signals in response to the second gray code.

15. The ADC converter of claim 14 , further comprising:
decoders configured to decode the comparison signals stored in at least the second latches.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Hyeok-Jong

Classifications

• H04N25/77 Primary

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H04N25/7795 Primary

  Circuitry for generating timing or clock signals · CPC title

• H03M1/123

  Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters · CPC title

• H04N5/3765

  Electricity · mapped topic