Integrated trench capacitor

Patent metadata

Field	Value
Publication number	US-10903306-B2
Application number	US-201816163606-A
Country	US
Kind code	B2
Filing date	Oct 18, 2018
Priority date	Sep 13, 2016
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

Embodiments of a deep trench capacitor are disclosed. In one example a plurality of deep trenches is located in a first region of a semiconductor wafer, the first region having a first conductivity type. A corresponding dielectric layer is located on a surface of each of the plurality of deep trenches, and a corresponding doped polysilicon filler is located within each of the dielectric layers. Dielectric-filled trenches are located between each of the dielectric layers and the surface of the semiconductor wafer.

First claim

What is claimed is:

1. An integrated circuit (IC), comprising:
a plurality of deep trenches in a first region of a semiconductor substrate, the first region being doped with a dopant of a first type;
a corresponding dielectric layer located on a sidewall surface of each deep trench;
a corresponding doped polysilicon filler located within each dielectric layer;
an oxide-filled trench located over each of the dielectric layers, the oxide-filled trench extending from the dielectric layer to a top surface of the semiconductor substrate;
wherein the first region includes a heavily-doped region located between a buried layer and the top surface of the semiconductor substrate.

2. The IC as recited in claim 1 wherein the first type of dopant is N-type and the substrate is doped with a P-type dopant.

3. The IC as recited in claim 1 wherein bottoms of the plurality of deep trenches are located within a buried layer within the semiconductor substrate.

4. The IC as recited in claim 1 wherein the heavily doped region is located in an epitaxial layer over the buried layer.

5. The IC as recited in claim 4 wherein the epitaxial layer is P-type, the semiconductor substrate is P-type, and the first region is N-type.

6. The IC as recited in claim 1 wherein the dielectric layer comprises a thermal oxide.

7. The IC as recited in claim 6 wherein the dielectric layer further comprises a nitrogen-containing layer over the thermal oxide.

8. The IC as recited in claim 7 wherein the dielectric layer further comprises an oxynitride layer over a nitride layer.

9. The IC as recited in claim 1 further comprising a contact to the first region and a contact to the polysilicon filler.

10. The IC as recited in claim 1 wherein the first region and the polysilicon filler are both doped with N-type dopants.

11. The IC as recited in claim 1 wherein the oxide-filled trench is about 400 nm thick.

12. The IC as recited in claim 1 wherein the deep trenches have a depth between about 5 μm and about 9 μm.

13. The IC as recited in claim 1 further comprising a plurality of contacts corresponding to the plurality of deep trenches, wherein only a single contact of the plurality of contacts is connected to each of the deep trenches.

14. The IC as recited in claim 1 wherein each of the plurality of deep trenches has a circular or oval cross-section.

15. The IC as recited in claim 1 wherein the first region includes a buried layer and a heavily-doped region located between the buried layer and the top surface of the semiconductor substrate.

16. The IC as recited in claim 1 wherein the polysilicon filler is N-type.

17. The IC as recited in claim 1 wherein the corresponding doped polysilicon filler extends to the top surface of the semiconductor substrate.

18. An electronic device, comprising:
a doped region having a first conductivity type located within a semiconductor substrate having a second opposite conductivity type, the doped region including a well region and a buried layer each having the first conductivity type;
a deep trench including an insulating sidewall layer and a doped polysilicon filler that extends from a top surface of the semiconductor substrate toward the buried layer; and
a shallow trench isolation (STI) structure that extends from the top surface of the semiconductor substrate to the insulating sidewall layer.

19. The device as recited in claim 18 wherein the dopant concentration in the well region is greater than the dopant concentration in the buried layer.

20. The device as recited in claim 18 wherein the substrate includes a P-type epitaxial layer in which the doped region is formed.

Assignees

• Texas Instruments Inc

Inventors

• Hu Binghua
• Kawahara Hideaki
• Pendharkar Sameer P

Classifications

• H10P52/402

  of semiconductor materials · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/6304

  Formation by oxidation, e.g. oxidation of the substrate · CPC title

• H10P14/416

  of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title