Array substrate and manufacturing method thereof, display device

Patent metadata

Field	Value
Publication number	US-10903249-B2
Application number	US-201816325158-A
Country	US
Kind code	B2
Filing date	Mar 29, 2018
Priority date	May 22, 2017
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

An array substrate including a plurality of terminals, a first conductive layer and a second conductive layer, wherein the first conductive layer and the second conductive layer include an insulating layer therebetween, wherein a plurality of first electrode plates and a plurality of second electrode plates are formed in the first conductive layer and the second conductive layer, respectively, the first electrode plates and the second electrode plates are opposite to each other to constitute a capacitor structure, the terminals are provided in the same layer as the first conductive layer or the second conductive layer, or the terminals are provided in the same layer as a third conductive layer between the first conductive layer and the second conductive layer. A method of manufacturing an array substrate and a display device is provided.

First claim

What is claimed is:

1. An array substrate comprising a plurality of terminals, a first conductive layer, a second conductive layer, and an insulating later between the first conductive layer and the second conductive layer, wherein
a plurality of first electrode plates and a plurality of second electrode plates are disposed in the first conductive layer and the second conductive layer, respectively, the first electrode plates and the second electrode plates being opposite to each other to form a capacitor structure, and wherein
the terminals are disposed in one of the following ways:
the terminals are disposed in the same layer as the first conductive layer or the second conductive layer; and
the terminals are disposed in the same layer as a third conductive layer between the first conductive layer and the second conductive layer,
wherein the first electrode plates and the second electrode plates comprise through holes exposing the terminals.

2. The array substrate according to claim 1 , wherein the terminals are provided in the same layer as the first conductive layer, and an insulating material is filled between the terminal and the first electrode plate.

3. The array substrate according to claim 1 , wherein the terminals are provided in the same layer as the third conductive layer between the first conductive layer and the second conductive layer, and leads of the terminals are disposed in the third conductive layer.

4. The array substrate according to claim 1 , wherein additional through holes are disposed at positions corresponding to the terminals in respective layers besides the first conductive layer above the terminals to expose the terminals.

5. A display device comprising the array substrate according to claim 1 .

6. The array substrate according to claim 1 , wherein the terminals are provided in the same layer as the second conductive layer, and wherein an insulating material is filled between the terminal and the second electrode plate.

7. The array substrate according to claim 2 , further comprising a fourth conductive layer, wherein leads of the terminals are disposed in the fourth conductive layer and connected to the terminals through vias.

8. The array substrate according to claim 2 , wherein additional through holes are disposed at positions corresponding to the terminals in respective layers besides the first conductive layer above the terminals to expose the terminals.

9. A display device comprising the array substrate according to claim 2 .

10. The array substrate according to claim 7 , wherein additional through holes are disposed at positions corresponding to the terminals in respective layers besides the first conductive layer above the terminals to expose the terminals.

11. A display device comprising the array substrate according to claim 7 .

12. The array substrate according to claim 3 , wherein additional through holes are disposed at positions corresponding to the terminals in respective layers besides the first conductive layer above the terminals to expose the terminals.

13. A display device comprising the array substrate according to claim 3 .

14. The array substrate according to claim 4 , wherein an orthographic projection of the through holes and the additional through holes on the base substrate of the array substrate at least partially covers the terminals.

15. The array substrate according to claim 14 , wherein the array substrate comprises the base substrate, a buffer layer, a TFT transistor, a planarization layer, an anode metal layer, a pixel defining layer, an organic light-emitting layer, and a cathode, wherein The TFT transistor comprises a source electrode, a drain electrode, a gate electrode, an active layer, and a gate insulating layer, and wherein the first conductive layer, the second conductive layer, and the third conductive layer are selected from at least one of the following layers:
the source electrode or the drain electrode, the gate electrode, the active layer, the anode metal layer, the organic light-emitting layer, and the cathode.

16. A method of manufacturing an array substrate comprising:
forming a plurality of first electrode plates in a first conductive layer;
forming a plurality of second electrode plates opposite to the first electrode plates respectively in a second conductive layer, wherein the first electrode plates and the second electrode plates constitute a capacitor structure; and
forming a plurality of terminals in the first conductive layer or the second conductive layer, or forming a plurality of terminals in a third conductive layer between the first conductive layer and the second conductive layer,
wherein the first electrode plates and the second electrode plates comprise through holes exposing the terminals.

17. The manufacturing method according to claim 16 , further comprising forming a plurality of terminals in the first conductive layer, wherein an insulating material is filled between the terminal and the first electrode plate.

18. The manufacturing method according to claim 16 , further comprising:
forming leads of the terminals in a fourth conductive layer, the leads of the terminals connected to the terminals through vias.

19. The manufacturing method according to claim 16 , wherein forming a plurality of terminals in a third conductive layer between the first conductive layer and the second conductive layer further comprises:
forming leads of the terminals in the third conductive layer.

20. The manufacturing method according to claim 16 , further comprising forming a plurality of terminals in the second conductive layer, wherein an insulating material is filled between the terminal and the second electrode plate.

Assignees

• Ordos Yuansheng Optoelectronics Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Zhang Wei
• Li Hui
• Shi Tianlei
• Kwak Jonguk
• Fang Yezhou
• Zhang Wenlong
• Zhang Xu
• Niu Zhijun
• Jiang Ruize
• Ren Yanwei
• Liu Yu

Classifications

• H10D89/911

  using passive elements as protective elements · CPC title

• H10D86/443

  adapted for preventing breakage, peeling or short circuiting · CPC title

• H10D86/021

  of multiple TFTs · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title