Thin film transistor substrate, display apparatus including thin film transistor substrate, method of manufacturing thin film transistor substrate, and method of manufacturing display apparatus

Patent metadata

Field	Value
Publication number	US-2016233253-A1
Application number	US-201514946805-A
Country	US
Kind code	A1
Filing date	Nov 20, 2015
Priority date	Feb 9, 2015
Publication date	Aug 11, 2016
Grant date	—

Abstract

A thin film transistor (TFT) substrate, including a substrate; a TFT on the substrate; and an insulating layer including at least one dummy hole, the at least one dummy hole in one or more of an upper area of the TFT or a peripheral area of the TFT, a material buried in the at least one dummy hole being an insulating material different from a material of the insulating layer.

First claim

What is claimed is:

1 . A thin film transistor (TFT) substrate, comprising:
a substrate; a TFT on the substrate; and an insulating layer including at least one dummy hole, the at least one dummy hole in one or more of an upper area of the TFT or a peripheral area of the TFT, a material buried in the at least one dummy hole being an insulating material different from a material of the insulating layer.

2 . The TFT substrate as claimed in claim 1 , wherein the insulating layer includes at least one contact hole in which a conductive material is buried.

3 . The TFT substrate as claimed in claim 2 , wherein a width of the at least one dummy hole has a substantially same width as the at least one contact hole.

4 . The TFT substrate as claimed in claim 2 , wherein:
the TFT includes an active pattern on the substrate and a gate electrode that overlaps at least one portion of the active pattern, the TFT substrate further includes a conductive layer that is electrically connected to the active pattern via the conductive material buried in the at least one contact hole, and the insulating layer is an interlayer insulating layer between the gate electrode and the conductive layer.

5 . The TFT substrate as claimed in claim 4 , further comprising a planarizing layer that covers the insulating layer and the conductive layer,
wherein a portion of the planarizing layer is buried in the at least one dummy hole.

6 . The TFT substrate as claimed in claim 4 , further comprising a gate insulating layer between the active pattern and the gate electrode,
wherein the at least one dummy hole includes a first dummy hole that penetrates through the gate insulating layer and extends to an upper surface of the substrate.

7 . The TFT substrate as claimed in claim 4 , wherein the at least one dummy hole includes a second dummy hole that extends to an upper surface of the gate electrode.

8 . The TFT substrate as claimed in claim 4 , further comprising:
a first gate insulating layer between the active pattern and the gate electrode, the first gate insulating layer including silicon oxide; and a second gate insulating layer between the first gate insulating layer and the gate electrode, the second gate insulating layer including silicon nitride.

9 . The TFT substrate as claimed in claim 4 , wherein the gate electrode includes aluminum (Al).

10 . The TFT substrate as claimed in claim 2 , wherein:
the TFT includes an active pattern on the substrate and a gate electrode that overlaps at least one portion of the active pattern, and the TFT substrate further includes: a first conductive layer on the gate electrode, the first conductive layer including an upper electrode that overlaps at least one portion of the gate electrode, wherein the upper electrode and the gate electrode form a capacitor; and a second conductive layer including a power line that is electrically connected to the upper electrode via the conductive material buried in the at least one contact hole, the power line applying a power voltage to the upper electrode, wherein the insulating layer is an interlayer insulating layer between the first and second conductive layers.

11 . The TFT substrate as claimed in claim 10 , further comprising a planarizing layer that covers the insulating layer and the second conductive layer,
wherein a portion of the planarizing layer is buried in the at least one dummy hole.

12 . The TFT substrate as claimed in claim 10 , further comprising:
a gate insulating layer between the active pattern and the gate electrode; and a dielectric layer between the gate electrode and the first conductive layer, wherein the at least one dummy hole includes a first dummy hole that penetrates through the gate insulating layer and the dielectric layer and extends to an upper surface of the surface.

13 . The TFT substrate as claimed in claim 10 , wherein the at least one dummy hole includes a second dummy hole that extends to an upper surface of the upper electrode.

14 . The TFT substrate as claimed in claim 1 , wherein:
the insulating layer includes an inorganic insulating material, and the material buried in the at least one dummy hole is an organic insulating material.

15 . The TFT substrate as claimed in claim 1 , wherein the dummy hole is circular, oval, or polygonal shaped.

16 . A display apparatus, comprising:
the thin film transistor (TFT) substrate as claimed in claim 1 ; and a display device on the TFT substrate.

17 . A method of manufacturing a thin film transistor (TFT) substrate, the method comprising:
forming a TFT on a substrate; forming an insulating layer including at least one dummy hole in one or more of an upper area of the TFT or a peripheral area of the TFT; and burying, in the at least one dummy hole, an insulating material different from a material of the insulating material.

18 . The method as claimed in claim 17 , wherein:
forming the insulating layer includes forming the insulating layer such that the insulating layer includes the at least one dummy hole and at least one contact hole, and the method further includes burying a conductive material in the at least one contact hole.

19 . The method as claimed in claim 18 , wherein forming the insulating layer includes forming the at least one dummy hole and at least one contact hole to have substantially a same width.

20 . The method as claimed in claim 18 , wherein:
forming the TFT includes forming an active pattern on the substrate, and forming a gate electrode such that the gate electrode overlaps at least one portion of the active pattern, burying the conductive material in the at least one contact hole includes forming a conductive layer electrically connected to the active pattern via the conductive material buried in the at least one contact hole, and forming the insulating layer includes forming an interlayer insulating layer between forming the gate electrode and forming the conductive layer.

21 . The method as claimed in claim 20 , further comprising forming a planarizing layer that covers the insulating layer and the conductive layer, wherein a portion of the planarizing layer is buried in the at least one dummy hole.

22 . The method as claimed in claim 20 , further comprising forming a gate insulating layer between forming the active pattern and forming the gate electrode,
wherein forming the insulating layer further includes forming a first dummy hole that penetrates through the gate insulating layer and extends to an upper surface of the substrate.

23 . The method as claimed in claim 20 , wherein forming the insulating layer includes:
coating an insulating material on the substrate; and forming a second dummy hole that extends to an upper surface of the gate electrode.

24 . The method as claimed in claim 17 , wherein:
forming the insulating layer includes forming an insulating layer that includes an inorganic insulating material, and the material buried in the at least one dummy hole is an organic insulating material.

25 . The method as claimed in claim 17 , wherein the dummy hole is circular, oval, or polygonal shaped.

26 . A method of manufacturing a display apparatus, the method comprising:
preparing a thin film transistor (TFT) substrate manufactured according to the method as claimed in claim 17 ; and forming a display device on the TFT substrate.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Hyunchul

Classifications

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/451 Primary

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title