Method for forming complementary doped semiconductor regions in a semiconductor body

Patent metadata

Field	Value
Publication number	US-10903079-B2
Application number	US-201916351256-A
Country	US
Kind code	B2
Filing date	Mar 12, 2019
Priority date	Mar 13, 2018
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

A method includes: forming first and second trenches in a semiconductor body; forming a first material layer on the semiconductor body in the first and second trenches such that a first residual trench remains in the first trench and a second residual trench remains in the second trench; removing the first material from the second trench; and forming a second material layer on the first material layer in the first residual trench and on the semiconductor body in the second trench. The first material layer includes dopants of a first doping type and the second material layer includes dopants of a second doping type. The method further includes diffusing dopants from the first material layer in the first trench into the semiconductor body to form a first doped region, and from the second material layer in the second trench into the semiconductor body to form a second doped region.

First claim

What is claimed is:

1. A method, comprising:
forming a first trench and a second trench in a semiconductor body;
forming a first material layer on the semiconductor body in the first trench and the second trench such that a first residual trench remains in the first trench and a second residual trench remains in the second trench, the first material layer including dopants of a first doping type;
removing the first material layer from the second trench;
forming a second material layer on the first material layer in the first residual trench and on the semiconductor body in the second trench, the second material layer including dopants of a second doping type, complementary to the first doping type; and
diffusing dopants from the first material layer in the first trench into the semiconductor body to form a first doped region, and from the second material layer in the second trench into the semiconductor body to form a second doped region.

2. The method of claim 1 , wherein one of the first material layer and the second material layer comprises BSG.

3. The method of claim 2 , wherein the other one of the first material layer and the second material layer comprises at least one of PSG and ASG.

4. The method of claim 1 , further comprising:
uncovering sections of a surface of the semiconductor body in the first trench; and
forming an electrically conducting layer on the uncovered sections of the surface of the semiconductor body in the first trench.

5. The method of claim 4 , wherein the uncovering the sections of the surface of the semiconductor body in the first trench comprises completely removing the first layer and the second layer from the first trench.

6. The method of claim 5 , wherein completely removing the first layer and the second layer from the first trench comprises:
forming an etch mask on top of the semiconductor body; and
removing the first layer and the second layer using a wet etching process.

7. The method of claim 6 , further comprising:
forming an oxide collar in an upper section of the first trench before forming the etch mask.

8. The method of claim 4 , wherein the electrically conducting layer comprises at least one of a metal and a doped polycrystalline semiconductor material.

9. The method of claim 1 , further comprising:
uncovering sections of a surface of the semiconductor body in the second trench; and
forming an electrically conducting layer on the uncovered sections of the surface of the semiconductor body in the second trench.

10. The method of claim 9 , wherein the uncovering the sections of the surface of the semiconductor body in the second trench comprises completely removing the second layer from the second trench.

11. The method of claim 10 , wherein completely removing the second layer from the second trench comprises:
forming an etch mask on top of the semiconductor body; and
removing the second layer using a wet etching process.

12. The method of claim 11 , further comprising:
forming an oxide collar in an upper section of the second trench before forming the etch mask.

13. The method of claim 9 , wherein the electrically conducting layer comprises at least one of a metal and a doped polycrystalline semiconductor material.

14. The method of claim 1 , wherein forming the first trench comprises forming two or more first trenches and forming the first doped region comprises forming two or more first doped regions, and wherein forming the second trench comprises forming two or more second trenches and forming the second doped region comprises forming two or more second doped regions.

15. The method of claim 14 , wherein a first one of the two or more first doped regions forms a source region of a transistor device, wherein a second one of the two or more first doped regions forms a drain region of the transistor device, and wherein the two or more second doped regions form gate regions of the transistor device.

16. The method of claim 14 , wherein a first one of the two or more second doped regions forms a source region of a transistor device, wherein a second one of the two or more second doped regions forms a drain region of the transistor device, and wherein the two or more first doped regions form gate regions of the transistor device.

17. The method of claim 1 , wherein the semiconductor body is arranged on a carrier and wherein at least one of the first trench and the second trench extends into the carrier.

18. The method of claim 17 , wherein the carrier at least in sections adjoining the semiconductor body comprises an electrically insulating material.

Assignees

• Infineon Tech Dresden Gmbh & Co Kg

Inventors

• Weis Rolf
• Gross Thomas
• Gruber Hermann
• Hirler Franz
• Meiser Andreas
• Rochel Markus
• Schloesser Till
• Weber Detlef

Classifications

• H10P32/00

  Diffusion of dopants within, into or out of wafers, substrates or parts of devices (during formation of materials H10P14/00) · CPC title

• H10P32/1412

  through the applied layer · CPC title

• H10P32/171 Primary

  being group IV material · CPC title

• H10P32/174

  being Group III-V material · CPC title

• H10P32/14

  within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title