Method for producing a semiconductor component with insulated semiconductor mesas

Patent metadata

Field	Value
Publication number	US-9396997-B2
Application number	US-201113288271-A
Country	US
Kind code	B2
Filing date	Nov 3, 2011
Priority date	Dec 10, 2010
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

A method for producing a semiconductor component is provided. The method includes providing a semiconductor body with a first surface and a second surface opposite to the first surface, etching an insulation trench from the first surface partially into the semiconductor body, forming a first insulation layer on one or more sidewalls of the insulation trench, processing the second surface by at least one of grinding, polishing and a CMP-process to expose the first insulation layer, and depositing on the processed second surface a second insulation layer which extends to the first insulation layer.

First claim

What is claimed is:

1. A method for producing a semiconductor component, comprising:
providing a semiconductor body with a first surface and a second surface opposite to the first surface;
forming an insulation trench from the first surface into the semiconductor body so that the insulation trench is, in a projection onto the first surface, substantially ring-shaped;
forming a first insulation layer at least on one or more sidewalls of the insulation trench so that the first insulation layer forms, in the projection onto the first surface, a first closed loop;
removing semiconductor material of the semiconductor body from the second surface to expose bottom portions of the first insulation layer and to form a back surface;
depositing a second insulation layer on the back surface such that at least two semiconductor mesas are formed which are insulated from each other by the first insulation layer and the second insulation layer;
forming a contact opening in the second insulation layer that extends to one of the at least two semiconductor mesas, such that the insulation trench remains covered by the second insulation layer at the back surface after the contact opening is formed in the second insulation layer;
forming an electrode that contacts the one of the at least two semiconductor mesas at the second surface through the contact opening, the electrode being separated from the insulation trench by the second insulation layer; and
forming a second insulation trench which forms, in the projection onto the first surface, a second closed loop within the first closed loop.

2. The method of claim 1 , wherein the second insulation layer comprises at least one of a boron-silicate glass, a spin-on glass, a silicone, a polymerized imide, a parylene or a polymerized benzocyclobutene, an organosilicate dielectric, a synthetic material, and a cured resin.

3. The method of claim 1 , wherein the insulation trench is completely filled with the first insulation layer.

4. The method of claim 1 , further comprising filling the insulation trench with a conductive material prior to depositing the second insulation layer.

5. The method of claim 4 , wherein the conductive material is selected from the group consisting of a doped amorphous semiconductor material, a doped polycrystalline semiconductor material, a metal, a silicide and carbon.

6. The method of claim 1 , wherein the second insulation layer is mask-less deposited on the back surface.

7. The method of claim 1 , wherein forming the insulation trench comprises a Bosch process.

8. The method of claim 1 , wherein the insulation trench forms a rectangular ring or an ellipsoidal ring.

9. The method of claim 1 , wherein removing semiconductor material of the semiconductor body comprises at least one of grinding, polishing, a CMP-process and etching.

10. The method of claim 1 , wherein the semiconductor body is thinned to a vertical thickness between the first surface and the back surface of less than about 50 μm by removing semiconductor material of the semiconductor body.

11. The method of claim 1 , wherein the semiconductor body comprises an epitaxial layer and wherein the insulation trench is etched completely through the epitaxial layer.

12. The method of claim 1 , wherein the semiconductor body is thinned to a vertical thickness between the first surface and the back surface by removing semiconductor material of the semiconductor body, wherein the insulation trench is etched to a vertical depth, and wherein the vertical thickness is about 5% to 30% smaller than the vertical depth.

13. The method of claim 1 , further comprising mounting the semiconductor body with the first surface on a carrier system prior to removing semiconductor material of the semiconductor body.

14. The method of claim 13 , wherein mounting the semiconductor body on the carrier system comprises attaching the semiconductor body to a glass substrate.

15. The method of claim 1 , further comprising at least one of:
forming a diode structure in at least one of the at least two semiconductor mesas;
forming a capacitance structure in or on at least one of the at least two semiconductor mesas;
forming a transistor structure in at least one of the at least two semiconductor mesas;
forming a gate electrode structure on the first surface and on at least one of the at least two semiconductor mesas;
forming a trench gate electrode structure extending form the first surface into at least one of the at least two semiconductor mesas; and;
forming on the first surface a wiring between the at least two semiconductor mesas and/or to the diode structure and/or to the capacitance structure and/or to the transistor structure and/or to the gate electrode structure and/or to the trench gate electrode structure.

16. The method of claim 1 , further comprising at least one of:
partially removing the second insulation layer to expose at least one of the at least two semiconductor mesas on the back side; and,
forming a metallization on the back side in ohmic contact with the at least one of the at least two semiconductor mesas.

17. The method of claim 1 , wherein the second insulation layer is deposited at a temperature below 400° C.

18. A method for producing a semiconductor component, comprising:
providing a semiconductor body with a first surface and a second surface opposite to the first surface;
etching an insulation trench from the first surface partially into the semiconductor body so that the insulation trench surrounds, in a projection onto the first surface, a semiconductor region of the semiconductor body;
forming a first insulation layer on one or more sidewalls of the insulation trench so that the first insulation layer forms, in the projection onto the first surface, a first closed loop;
filling the insulation trench with a conductive material;
processing the second surface comprising at least one of grinding, polishing, a CMP-process and etching to expose the first insulation layer;
depositing on the processed second surface a second insulation layer which extends to the first insulation layer;
forming a contact opening in the second insulation layer that extends to the processed second surface, such that the insulation trench remains covered by the second insulation layer at the second surface after the contact opening is formed in the second insulation layer;
forming an electrode that contacts the processed second surface through the contact opening, the electrode being separated from the insulation trench by the second insulation layer; and
forming a second insulation trench which forms, in the projection onto the first surface, a second closed loop within the first closed loop.

19. The method of claim 18 , wherein at least two semiconductor mesas are formed in the semiconductor body which are laterally insulated from each other by the first insulation layer.

20. The method of claim 19 , wherein at least one of the two semiconductor mesas is completely insulated on the processed second surface by the second insulation layer after finishing processing the semiconductor component.

21. The method of claim 19 , further comprising prior to processing the second surface at least one of:
forming an electric component in or on at least one of the at least two semiconductor mesas; and,
forming on the first surface a wiring between the at least two semiconductor mesas and/or to the electric component.

22. The method of claim 18 , further comprising finishin

Assignees

• Hirler Franz
• Mauder Anton
• Gruber Hermann
• Rothleitner Hubert
• Meiser Andreas Peter
• Infineon Technologies Ag

Inventors

• Hirler Franz
• Mauder Anton
• Gruber Hermann
• Rothleitner Hubert
• Meiser Andreas Peter

Classifications

• H10W90/726

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title