Asymmetric gate spacer formation using multiple ion implants

Patent metadata

Field	Value
Publication number	US-10896855-B2
Application number	US-201916436296-A
Country	US
Kind code	B2
Filing date	Jun 10, 2019
Priority date	Jun 10, 2019
Publication date	Jan 19, 2021
Grant date	Jan 19, 2021

Abstract

Disclosed are methods for forming a semiconductor device. In some embodiments, a method may include providing a gate structure atop a substrate, providing a gate spacer along a sidewall of the gate structure, and performing a first ion implant to the gate structure and the gate spacer, the first ion implant comprising a thermal implant disposed at a first non-zero angle of inclination with respect to a perpendicular to a plane of the substrate. The method may further include performing a second ion implant to the gate structure and the gate spacer, the second ion implant including a room-temperature ion implant disposed at a second non-zero angle of inclination with respect to the perpendicular to the plane of the substrate, and etching the gate structure and the gate spacer to remove just the second section of the gate spacer.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
providing a gate structure atop a substrate;
providing a gate spacer along a sidewall of the gate structure;
performing a first ion implant to the gate structure and the gate spacer, the first ion implant disposed at a first non-zero angle of inclination with respect to a perpendicular to a plane of the substrate;
performing a second ion implant to the gate structure and the gate spacer, the second ion implant disposed at a second non-zero angle of inclination with respect to the perpendicular to the plane of the substrate, wherein the first ion implant is performed at a temperature greater than 500° C. and the second ion implant is performed at a temperature between approximately 15° C. and 30° C.; and
etching the gate spacer to remove just one section of the gate spacer selective to a top surface of the substrate and to a sidewall surface of the gate structure.

2. The method of claim 1 , further comprising etching the gate spacer using a dilute hydrofluoric acid solution.

3. The method according to claim 1 , wherein the gate structure is a dummy gate electrode, and wherein the gate spacer is a silicon nitride spacer.

4. The method according to claim 1 , further comprising rotating the substrate 180° between the first ion implant and the second ion implant.

5. The method according to claim 1 , wherein the first ion implant includes at least one of: argon ions and helium ions.

6. The method according to claim 1 , wherein the first ion implant and the second ion implant include argon ions.

7. A method of forming an asymmetric gate spacer, the method comprising:
providing a gate structure atop a substrate;
providing a first gate spacer along a first sidewall of the gate structure, and providing a second gate spacer along a second sidewall of the gate structure;
performing a first ion implant to the first gate spacer, the first ion implant disposed at a first non-zero angle of inclination with respect to a perpendicular to a plane of the substrate, wherein the first ion implant is performed at a temperature greater than 500° C.;
performing a second ion implant to the second gate spacer, the second ion implant disposed at a second non-zero angle of inclination with respect to the perpendicular to the plane of the substrate, wherein the second ion implant is performed at a temperature between approximately 15° C. and 30° C.; and
etching the first gate spacer and the second gate spacer, wherein just the second gate spacer is removed selective to a top surface of the substrate and to a sidewall surface of the second sidewall of the gate structure.

8. The method of claim 7 , further comprising etching the first gate spacer and the second gate spacer using a dilute hydrofluoric acid solution.

9. The method according to claim 7 , wherein the gate structure is a dummy gate electrode, and wherein the first and second gate spacers are silicon nitride spacers.

10. The method according to claim 7 , wherein the first and second ion implants include at least one of: argon ion and helium ions.

11. A method of forming an asymmetric gate spacer, the method comprising:
providing a dummy gate structure atop a substrate;
providing a first gate spacer along a first sidewall of the dummy gate structure, and providing a second gate spacer along a second sidewall of the dummy gate structure; performing a first ion implant to the first gate spacer, the first ion implant disposed at a first non-zero angle of inclination with respect to a perpendicular to a plane of the substrate, wherein the first ion implant is performed at a platen temperature greater than 500° C.;
performing a second ion implant to the second gate spacer, the second ion implant disposed at a second non-zero angle of inclination with respect to the perpendicular to the plane of the substrate, wherein the second ion implant is performed at a temperature between approximately 15° C. and 30° C.; and
etching the first gate spacer and the second gate spacer, wherein just the second gate spacer is removed selective to a top surface of the substrate and to a sidewall surface of the second sidewall of the dummy gate structure.

12. The method according to claim 11 , further comprising etching the first gate spacer and the second gate spacer using a dilute hydrofluoric acid solution.

13. The method according to claim 11 , wherein the first and second gate spacers are silicon nitride spacers.

14. The method according to claim 11 , wherein the first and second ion implants include at least one of: argon ions and helium ions.

15. The method according to claim 11 , further comprising rotating the substrate approximately 180° between the first ion implant and the second ion implant.

Assignees

• Applied Materials Inc

Inventors

• Waite Andrew M

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P50/283

  by chemical means · CPC title

• H10D84/0147

  Manufacturing their gate sidewall spacers · CPC title

• H10D64/015

  removing at least parts of gate spacers, e.g. disposable spacers · CPC title

• H10D84/038 Primary

  using silicon technology, e.g. SiGe · CPC title