Tag-based wear leveling for a data storage device

Patent metadata

Field	Value
Publication number	US-2016170682-A1
Application number	US-201414572693-A
Country	US
Kind code	A1
Filing date	Dec 16, 2014
Priority date	Dec 16, 2014
Publication date	Jun 16, 2016
Grant date	—

Abstract

A data storage device includes a memory. A method includes de-allocating a first region of a group of regions of the memory during a wear leveling process based on a determination that the first region is associated with a first tag of a set of tags. Each region of the group of regions is assigned to a tag of the set of tags based on a health metric associated with the region. The health metric is based on a bit error rate (BER), a program/erase cycle (PEC) count, a PEC condition metric, or a combination thereof. In response to selecting the first region, information is copied from the first region to a second region of the memory during the wear leveling process.

First claim

What is claimed is:

1 . A method comprising:
in a data storage device that includes a memory, performing:
during a wear leveling process, de-allocating a first region of a group of regions of the memory based on a determination that the first region is associated with a first tag of a set of tags, each region of the group of regions assigned to a tag of the set of tags based on a health metric associated with the region, wherein the health metric is based on a bit error rate (BER), a program/erase cycle (PEC) count, a PEC condition metric, or a combination thereof; and
in response to selecting the first region, copying information from the first region to a second region of the memory during the wear leveling process.

2 . The method of claim 1 , wherein the first tag statistically indicates an approximate duration that the information has been stored at the first region, and further comprising allocating the second region to allocated blocks of the memory based on a determination that a free block list indicates that the second region is frequently accessed.

3 . The method of claim 1 , wherein the first tag is the numerically lowest tag of the set of tags.

4 . The method of claim 1 , wherein the first region and at least a third region of the memory are both associated with the first tag.

5 . The method of claim 4 , further comprising comparing a first number of PECs of the first region to a second number of PECs of the second region in response to determining that the first region and the third region are associated with the first tag.

6 . The method of claim 5 , wherein the first region is selected for the wear leveling process in response to determining that the first number is less than the second number.

7 . The method of claim 5 , further comprising comparing a first BER of the first region to a second BER of the second region in response to determining that the first number is equal to the second number.

8 . The method of claim 7 , wherein the first region is selected for the wear leveling process in response to determining that the first number is less than the second number.

9 . The method of claim 7 , further comprising comparing a first PEC condition metric of the first region to a second PEC condition metric of the second region in response to determining that the first BER is equal to the second BER.

10 . The method of claim 9 , wherein the first PEC condition metric indicates a programming voltage applied to storage elements of the first region, and wherein the second PEC condition metric indicates a programming voltage applied to storage elements of the second region.

11 . The method of claim 9 , wherein the first region is selected for the wear leveling process in response to determining that the first PEC condition metric is less than the second PEC condition metric.

12 . The method of claim 1 , further comprising selecting the second region based on a free block list indicating that the second region is less healthy than other regions indicated by the free block list.

13 . The method of claim 12 , further comprising updating the free block list by adding a first indication of the first region and by deleting a second indication of the second region.

14 . The method of claim 1 , wherein the data storage device further includes a controller coupled to the memory, and wherein the wear leveling process is initiated by the controller.

15 . The method of claim 1 , wherein the memory has a three-dimensional (3D) memory configuration that is monolithically formed in one or more physical levels of arrays of memory cells having an active area above a silicon substrate.

16 . A data storage device comprising:
a memory; and a controller coupled to the memory, wherein the controller is configured to de-allocate a first region of a group of regions of the memory during a wear leveling process, the first region de-allocated based on a determination that the first region is associated with a first tag of a set of tags, each region of the group of regions assigned to a tag of the set of tags based on a health metric associated with the region, wherein the health metric is based on a bit error rate (BER), a program/erase cycle (PEC) count, a PEC condition metric, or a combination thereof, and wherein the controller is further configured to copy information from the first region to a second region of the memory during the wear leveling process in response to selecting the first region.

17 . A data storage device comprising:
a memory; and a controller coupled to the memory, wherein the controller is configured to maintain a set of tags, wherein the controller is configured to select a region of the memory for a wear leveling process based on the region being associated with a particular tag of the set of tags, and wherein the controller is further configured to select a programming voltage for a write operation associated with the region based on the region being associated with the particular tag.

18 . The data storage device of claim 17 , wherein the controller is further configured to reassign a first region of the memory from a first tag of the set of tags to a second tag of the set of tags based on a parameter associated with the first region satisfying a threshold.

19 . The data storage device of claim 18 , wherein the parameter is a health metric that is based on a bit error rate (BER) associated with the first region, a program/erase cycle (PEC) count associated with the first region, a PEC condition metric associated with the first region, or a combination thereof.

20 . The data storage device of claim 17 , wherein the memory has a three-dimensional (3D) memory configuration that is monolithically formed in one or more physical levels of arrays of memory cells having an active area above a silicon substrate, and further comprising circuitry associated with operation of the memory cells.

Assignees

• Sandisk Technologies Inc

Inventors

• Bakshi Swati
• Yang Nian Niles
• Naberezhnov Alexei
• Hu Xinde

Classifications

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0616 Primary

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0644

  Management of space entities, e.g. partitions, extents, pools · CPC title

• G06F3/0649 Primary

  Lifecycle management · CPC title