Virtual inductors using ferroelectric capacitance and the fabrication method thereof

Patent metadata

Field	Value
Publication number	US-10892728-B2
Application number	US-201816226747-A
Country	US
Kind code	B2
Filing date	Dec 20, 2018
Priority date	Dec 20, 2018
Publication date	Jan 12, 2021
Grant date	Jan 12, 2021

Abstract

Devices, system and methods a circuit, including a resistor, a normal capacitor and a ferroelectric capacitor connected in series. An input terminal to provide an input voltage across the circuit. An output terminal to deliver an output voltage taken across the normal capacitor. The circuit comprises a ferroelectric layer sandwiched between a first buffer layer and a second buffer layer. The first buffer layer contacts a portion of a first metal layer and first metal layer extends beyond the first buffer layer. A dielectric layer sandwiched between a second metal layer and a third metal layer. Such that the second metal layer extends beyond the dielectric layer and in contact with the second buffer layer. Wherein the ferroelectric capacitor is formed by the first metal layer. The ferroelectric layer sandwiched between the first buffer layer and the second buffer layer, and the second metal layer.

First claim

What is claimed is:

1. A circuit, comprising:
a resistor, a normal capacitor and a ferroelectric capacitor are connected in series;
an input terminal to provide an input voltage across the circuit; and
an output terminal to deliver an output voltage taken across the normal capacitor, across the ferroelectric capacitor or across the normal capacitor and the ferroelectric capacitor, such that the circuit behaves as a resonant circuit, wherein the circuit is an integrated circuit formed on a substrate, the circuit comprises:
a ferroelectric layer sandwiched between a first buffer layer and a second buffer layer, wherein the first buffer layer contacts a portion of a surface of a first metal layer and the first metal layer extends beyond the first buffer layer; and
a dielectric layer sandwiched between a second metal layer and a third metal layer, such that the second metal layer extends beyond the dielectric layer and in contact with the second buffer layer, wherein the ferroelectric capacitor is formed by the first metal layer and the second metal layer, and wherein the normal capacitor is formed by the dielectric layer and the third metal layer.

2. The circuit of claim 1 , wherein the ferroelectric layer is a Ferroelectric Oxide (FEO) layer, and the first buffer layer and the second buffer layer are metallic.

3. The circuit of claim 2 , wherein a thickness of the FEO layer is less than a critical thickness T c determined based on
T c =1/(2α C cap ),

wherein α is a material based parameter of the FEO layer, C cap is a capacitance of the normal capacitor.

4. The circuit of claim 2 , wherein the FEO layer includes one or combination of Barium titanate (BaTiO 3 ), Strontium titanate (SrTiO3), Hafnium Zirconium Oxide (HfZrOx) and Doped Hafnium oxide.

5. The circuit of claim 2 , wherein a material of the FEO layer is doped.

6. The circuit of claim 1 , wherein the first buffer layer and the second buffer layer are one of same materials or different materials, such that at least one material is a ceramic material including Titanium Nitride (TiN).

7. The circuit of claim 1 , wherein the first metal layer is arranged on the substrate.

8. The circuit of claim 1 , wherein a total lateral area of a combined rectangular prism is equal to a combined cubic foot of the third metal layer and the dielectric layer, the dielectric layer having a lateral area which is less than a total lateral area of a second combined rectangular prism that is a combined cubic foot of the second metal layer, the first buffer layer, the ferroelectric layer, the second buffer layer and the first metal layer.

9. The circuit of claim 1 , wherein at least one dimension of the dielectric layer is selected based on a function of a resonance frequency in the circuit.

10. The circuit of claim 9 , wherein the at least one dimension includes a thickness of the dielectric layer, a lateral area of the dielectric layer, or both.

11. The circuit of claim 10 , wherein a change in at least one of the dimensions of the dielectric layer directly corresponds to a change in a working frequency range of the circuit, which corresponds to a change in a capacitance of the circuit, which corresponds to a change in the resonance frequency in the circuit.

12. A circuit, comprising:
a resistor, a normal capacitor and a ferroelectric capacitor are connected in series;
an input terminal to provide an input voltage across the circuit; and
an output terminal to deliver an output voltage taken across the normal capacitor, across the ferroelectric capacitor or across the normal capacitor and the ferroelectric capacitor, and the first metal layer and third metal layer serve as the input terminal, and second metal layer and third metal layer serve as the output terminal, wherein the circuit is an integrated circuit formed on a substrate, the circuit comprises:
a ferroelectric layer sandwiched between a first buffer layer and a second buffer layer, wherein the first buffer layer contacts a portion of a surface of a first metal layer and the first metal layer extends beyond the first buffer layer; and

a dielectric layer sandwiched between a second metal layer and a third metal layer, such that the second metal layer laterally extends beyond the dielectric layer and in contact with the second buffer layer, wherein the ferroelectric capacitor is formed by the first metal layer and the second metal layer, and wherein the normal capacitor is formed by the dielectric layer and the third metal layer.

13. A device, comprising:
a circuit including a resistor, a normal capacitor and a ferroelectric capacitor are connected in series;
an input terminal to provide an input voltage across the circuit; and
an output terminal to deliver an output voltage taken across the normal capacitor, across the ferroelectric capacitor or across the normal capacitor and the ferroelectric capacitor, such that the circuit behaves as a resonant circuit, wherein the circuit is an integrated circuit formed on a substrate, the circuit comprises:
a ferroelectric layer sandwiched between a first buffer layer and a second buffer layer, wherein the first buffer layer contacts a portion of a surface of a first metal layer and the first metal layer extends beyond the first buffer layer; and
a dielectric layer sandwiched between a second metal layer and a third metal layer, such that the second metal layer extends beyond the dielectric layer and in contact with the second buffer layer, wherein the ferroelectric capacitor is formed by the first metal layer and the second metal layer, and a thickness of the ferroelectric layer is in a range of 5 nm to 30 nm, wherein the normal capacitor is formed by the dielectric layer and the third metal layer.

14. The device of claim 13 , wherein the ferroelectric layer is Zr-doped HfO2, and a thickness of at least one buffer layer of the first and the second buffer layers is in a range of 5 nm to 50 nm, and a thickness of the dielectric layer is in a range of 5 nm to 50 nm.

15. The device of claim 13 , wherein one or more of the devices are electrically connected to one or more resistors and one or more capacitors to form an analog matching circuit so as for impedance matching for an output of the circuit to an input of another circuit.

Assignees

• Mitsubishi Electric Res Laboratories Inc

Inventors

• Teo Koon Hoo
• Shen Pin Chun
• Lin Chungwei

Classifications

• H10D1/694

  comprising noble metals or noble metal oxides · CPC title

• H10D84/02

  characterised by using material-based technologies · CPC title

• H10D1/682 Primary

  having dielectrics comprising perovskite structures · CPC title

• H10D84/60 Primary

  characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs (H10D84/40 takes precedence) · CPC title

• H03H7/06

  including resistors (H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence) · CPC title