Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination

Patent metadata

Field	Value
Publication number	US-9665462-B2
Application number	US-201514883377-A
Country	US
Kind code	B2
Filing date	Oct 14, 2015
Priority date	Oct 14, 2015
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

An arbitration system and method is disclosed. The apparatus includes first and second memory devices, and a resistor coupled in common to the first and second memory devices, the first memory device including a first calibration circuit configured to perform, when activated, a first calibration operation based on the resistor and a first arbiter configured to activate the first calibration circuit responsive, at least in part, to an assertion of a first command or keep the first calibration circuit inactive irrespective of the assertion of the first command.

First claim

The invention claimed is:

1. An apparatus comprising:
first and second memory devices; and
a resistor coupled in common to the first and second memory devices;
the first memory device comprising a first calibration circuit configured to perform, when activated, a first calibration operation based on the resistor and a first arbiter configured to activate the first calibration circuit responsive, at least in part, to an assertion of a first command or keep the first calibration circuit inactive irrespective of the assertion of the first command; and
the second memory device comprising a second calibration circuit configured to perform, when activated, a second calibration operation based on the resistor and a second arbiter configured to activate the second calibration circuit responsive, at least in part, to an assertion of a second command or keep the second calibration circuit inactive irrespective of the assertion of the second command.

2. The apparatus of claim 1 , wherein the first memory device and the second memory device are packaged independently of each other.

3. The apparatus of claim 1 , wherein the first memory device and the second memory device are packaged in one package.

4. The apparatus of claim 1 , further comprising a ring-shaped bus on which the first arbiter and the second arbiter are serially coupled and an enable signal is transmitted, wherein the first arbiter is configured to activate the first calibration circuit responsive, at least in part, to the assertion of the first command while keeping the enable signal therein and configured to keep the first calibration circuit inactive irrespective of the assertion of the first command when free from the enable signal and the second arbiter is configured to activate the second calibration circuit responsive, at least in part, to the assertion of the second command while keeping the enable signal therein and configured to keep the second calibration circuit inactive irrespective of the assertion of the second command when free from the enable signal.

5. The apparatus of claim 4 , wherein the first arbiter is configured to keep the enable signal for a predetermined time in the event that the enable signal is received at the first memory device prior to the first command being received at the first memory device and the second arbiter is configured to keep the enable signal for a predetermined time in the event that the enable signal is received at the second memory device prior to the first command being received at the second memory device.

6. The apparatus of claim 4 , wherein the first arbiter includes a first latch configured to receive and store the enable signal response to a first activation signal and the second arbiter includes a second latch configured to receive and store the enable signal response to a second activation signal.

7. The apparatus of claim 1 , wherein the first arbiter includes a first voltage sensor configured to detect a first voltage of a first terminal coupled to the resistor and the second arbiter includes a second voltage sensor configured to detect a second voltage of a second terminal coupled to the resistor, the first arbiter being configured to activate the first calibration circuit responsive, at least in part, to the assertion of the first command when the first voltage sensor detects that the first voltage is in a first voltage range and configured to keep the first calibration circuit inactive irrespective of the assertion of the first command when the first voltage sensor detects that the first voltage is in a second voltage range, the second arbiter being configured to activate the second calibration circuit responsive, at least in part, to the assertion of the second command when the second voltage sensor detects that the second voltage is in the first voltage range and configured to keep the second calibration circuit inactive irrespective of the assertion of the second command when the second voltage sensor detects that the second voltage is in the second voltage range.

8. The apparatus of claim 7 , wherein, in the event that the first voltage is in the second voltage range, the first arbiter is configured to refrain from further voltage detection on the resistor for a first back-off time assigned to the first arbiter and, in the event that the second voltage is in the second voltage range, the second arbiter is configured to refrain from further voltage detection on the resistor for a second back-off time assigned to the second arbiter.

9. The apparatus of claim 8 , further comprising a first delay generator configured to assign the first back-off time to the first arbiter based on a first random number and a second delay generator configured to assign the second back-off time to the second arbiter based on a second random number.

10. The apparatus of claim 9 , wherein the first delay generator includes a first plurality of metastable sense amplifiers configured to generate the first random number, the first random number used by a first plurality of RC delay blocks to form a first aggregate delay that is used to determine the first back-off time, and wherein the second delay generator includes a second plurality of metastable sense amplifiers configured to generate the second random number, the second random number used by a second plurality of RC delay blocks to form a second aggregate delay that is used to determine the second back-off time.

11. The apparatus of claim 9 , wherein the first delay generator is configured to determine the first back-off time which is stable during the operation of the first memory device and the second delay generator is configured to determine the second back-off time which is stable during the operation of the second memory device.

Assignees

• Micron Technology Inc

Inventors

• Tatapudi Suryanarayana
• Ayyapureddi Sujeet

Classifications

• G11C8/10

  Decoders · CPC title

• G11C8/06

  Address interface arrangements, e.g. address buffers · CPC title

• G06F11/348 Primary

  Circuit details, i.e. tracer hardware · CPC title

• G06F11/3037

  where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00) · CPC title

• G11C7/1066

  Output synchronization · CPC title