Apparatus and method for efficient graphics virtualization

Patent metadata

Field	Value
Publication number	US-10891773-B2
Application number	US-201715482677-A
Country	US
Kind code	B2
Filing date	Apr 7, 2017
Priority date	Apr 7, 2017
Publication date	Jan 12, 2021
Grant date	Jan 12, 2021

Abstract

An apparatus and method are described for allocating local memories to virtual machines. For example, one embodiment of an apparatus comprises: a command streamer to queue commands from a plurality of virtual machines (VMs) or applications, the commands to be distributed from the command streamer and executed by graphics processing resources of a graphics processing unit (GPU); a tile cache to store graphics data associated with the plurality of VMs or applications as the commands are executed by the graphics processing resources; and tile cache allocation hardware logic to allocate a first portion of the tile cache to a first VM or application and a second portion of the tile cache to a second VM or application; the tile cache allocation hardware logic to further allocate a first region in system memory to store spill-over data when the first portion of the tile cache and/or the second portion of the file cache becomes full.

First claim

What is claimed is:

1. A processor comprising:
a command streamer to queue commands from a plurality of virtual machines (VMs), the commands to be distributed from the command streamer and executed by graphics processing resources of a graphics processing unit (GPU);
a tile cache to store graphics data associated with the plurality of VMs as the commands are executed by the graphics processing resources; and
tile cache allocation hardware logic to allocate a first portion of the tile cache to a first VM and a second portion of the tile cache to a second VM, wherein a priority associated with each of the plurality of VMs and sizes of the first portion and second portion of the tile cache are selected in accordance with the priorities;
the tile cache allocation hardware logic to further allocate a first region in system memory to store spill-over data for the first VM when the first portion of the tile cache allocated to the first VM becomes full and the second portion of the tile cache allocated to the second VM is available.

2. The processor as in claim 1 wherein the tile cache allocation hardware logic comprises circuitry and/or logic to determine whether requested data is stored in the tile cache and, if not, to send a request to the first region in memory.

3. The processor as in claim 1 wherein the tile cache allocation hardware logic is to allocate a relatively larger size for the first portion than the second portion if the first VM has a relatively higher priority than the second VM.

4. The processor as in claim 1 further comprising:
a shared local memory (SLM) to be shared by the first VM and the second VM; and
an SLM controller to allocate a first portion of the SLM to the first VM and a second portion of the SLM to the second VM;
the SLM controller to further allocate a second region in the system memory to store spill-over data when at least one of the first portion of the SLM and the second portion of the SLM becomes full.

5. The processor as in claim 4 wherein the SLM controller comprises circuitry and/or logic to determine whether requested data is stored in the SLM and, if not, to send a request to the second region in memory.

6. The processor as in claim 4 wherein the SLM controller comprises prioritization logic to determine a priority associated with each of the plurality of VMs and to determine a size of the first portion and second portion of the SLM in accordance with the priorities.

7. The processor as in claim 6 wherein the SLM controller is to allocate a relatively larger size for the first portion than the second portion of the SLM if the first VM has a relatively higher priority than the second VM.

8. The processor as in claim 1 wherein the graphics processing resources are subdivided into a plurality of slices, the processor further comprising:
a power/performance management unit to independently set at least one of voltage and frequency provided to each of the plurality of slices based on identifying the slices used to process the first and second VMs and priorities associated with the first VM and the second VM.

9. The processor as in claim 1 , wherein one or more counters are programmed in accordance with relative priorities of the plurality of VMs.

10. The processor as in claim 9 , wherein the one or more counters count numbers of VM access to a memory fabric.

11. The processor as in claim 9 , wherein the one or more counters count numbers of elapsed cycles.

12. The processor as in claim 1 , wherein storing the spill-over data in the system memory comprises translating guest virtual addresses of the first VM to guest page numbers, and translating the guest page numbers to physical page numbers.

13. The processor as in claim 1 , wherein the first region is to store spill-over data for the second VM when the second portion of the tile cache allocated to the second VM becomes full and the first portion of the tile cache allocated to the first VM is available.

14. The processor as in claim 13 , wherein the first VM is to store the spill-over data using a first base address, and the second VM is to store the spill-over data using a second base address different from the first base address.

15. A method comprising:
queuing commands from a plurality of virtual machines (VMs), the commands to be distributed and executed by graphics processing resources of a graphics processing unit (GPU);
storing graphics data associated with the plurality of VMs in a tile cache as the commands are executed by the graphics processing resources;
allocating a first portion of the tile cache to a first VM and a second portion of the tile cache to a second VM, wherein a priority associated with each of the plurality of VMs and sizes of the first portion and second portion of the tile cache are selected in accordance with the priorities; and
allocating a first region in system memory to store spill-over data for the first VM when the first portion of the tile cache allocated to the first VM becomes full and the second portion of the tile cache allocated to the second VM is available.

16. The method as in claim 15 further comprising:
determining whether requested data is stored in the tile cache and, if not, sending a request to the first region in memory.

17. The method as in claim 15 wherein a relatively larger size is to be allocated for the first portion compared to the second portion if the first VM has a relatively higher priority than the second VM.

18. The method as in claim 15 further comprising:
allocating a first portion of a shared local memory (SLM) to the first VM and a second portion of the SLM to the second VM; and
allocating a second region in the system memory to store spill-over data when at least one of the first portion of the SLM and the second portion of the SLM becomes full.

19. The method as in claim 18 further comprising:
determining whether requested data is stored in the SLM and, if not, sending a request to the second region in memory.

20. The method as in claim 18 further comprising:
determining a priority associated with each of the plurality of VMs; and
selecting a size of the first portion and second portion of the SLM in accordance with the priorities.

21. The method as in claim 20 further comprising:
allocating a relatively larger size for the first portion than the second portion of the SLM if the first VM has a relatively higher priority than the second VM.

22. The method as in claim 15 wherein the graphics processing resources are subdivided into a plurality of slices, the method further comprising:
independently setting at least one of voltage and frequency provided to each of the plurality of slices based on identifying the slices used to process the first and second VMs and priorities associated with the first VM and the second VM.

23. A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform:
queuing commands from a plurality of virtual machines (VMs), the commands to be distributed and executed by graphics processing resources of a graphics processing unit (GPU);
storing graphics data associated with the plurality of VMs in a tile cache as the commands are executed by the graphics processing resources;
allocating a first portion of the tile cache to a first VM and a second portion of the tile cache to a second VM, wherein a priority associated with each of the plurality of VMs and sizes of the

Assignees

• Intel Corp

Inventors

• Ray Joydeep
• Appu Abhishek R
• K Pattabhiraman
• Vembu Balaji
• Koker Altug
• Cooray Niranjan L
• Mastronarde Josh B

Classifications

• G06F9/45554 Primary

  Instruction set architectures of guest OS and hypervisor or native processor differ, e.g. Bochs or VirtualPC on PowerPC MacOS · CPC title

• G06F9/45508

  Runtime interpretation or emulation, e g. emulator loops, bytecode interpretation · CPC title

• G06F2009/4557

  Distribution of virtual machine instances; Migration and load balancing · CPC title

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title

• G06F2212/455

  Image or video data · CPC title