Method and system for providing shared memory access to graphics processing unit processes

Patent metadata

Field	Value
Publication number	US-9547535-B1
Application number	US-43379709-A
Country	US
Kind code	B1
Filing date	Apr 30, 2009
Priority date	Apr 30, 2009
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

One or more embodiments of the invention set forth techniques to create a process in a graphical processing unit (GPU) that has access to memory buffers in the system memory of a computer system that are shared among a plurality of GPUs in the computer system. The GPU of the process is able to engage in Direct Memory Access (DMA) with any of the shared memory buffers thereby eliminating additional copying steps that have been needed to combine data output of the various GPUs without such shared access.

First claim

I claim:

1. A computer-implemented method for creating a first process that executes on a first graphics processing unit (GPU) within a plurality of GPUs included in a computer system, the method comprising:
maintaining a list of a set of processes executing on the plurality of GPUs, wherein the set of processes includes the first process;
maintaining a list of address range entries, wherein each address range entry in the list of address range entries comprises an address range corresponding to a different shared memory buffer in a set of shared memory buffers;
requesting that an address space be allocated in the first GPU for the first process;
requesting that the first GPU map the address range associated with each of the address range entries in the list of address range entries into the allocated address space, wherein a first address range is associated with a pinned memory buffer that is mapped into a second address space allocated in a second GPU within the plurality of GPUs; and
adding the first process to the list of the set of processes, wherein the first process has access to any shared memory buffer corresponding to at least one of the address ranges mapped into the allocated address space.

2. The method of claim 1 , wherein the list of the set of processes and the list of address range entries are red black tree data structures.

3. The method of claim 1 , wherein the list of the set of processes and the list of address range entries are maintained in the system memory.

4. The method of claim 1 , wherein each of the shared memory buffers in the set of shared memory buffers is a page-locked memory buffer.

5. The method of claim 1 , wherein the first GPU accesses any of the shared memory buffers in the set of shared memory buffers via a direct memory access operation.

6. The method of claim 1 , further comprising receiving a request to create the first process in the first GPU from an application executing on the computer system.

7. The method of claim 6 , further comprising the step of transmitting a notification to the application that the first process has been successfully created.

8. The method of claim 1 , wherein each GPU included in the plurality of GPUs maintains a separate page table that maps a different virtual address space associated with the respective GPU to the set of shared memory buffers.

9. The method of claim 8 , wherein each process in the set of processes is configured to directly access the set of shared memory buffers via the page table corresponding to the GPU included in the plurality of GPUs upon which the process is executing.

10. A non-transitory computer-readable medium including instructions that, when executed by a processing unit, causes the processing unit to create a first process that executes on a first graphics processing unit (GPU) within a plurality of GPUs of a computer system, by performing the steps of:
maintaining a list of a set of processes executing on the plurality of GPUs, wherein the set of processes includes the first process;
maintaining a list of address range entries, wherein each address range entry in the list of address range entries comprises an address range corresponding to a different shared memory buffer in a set of shared memory buffers;
requesting that an address space be allocated in the first GPU for the first process;
requesting that the first GPU map the address range associated with each of the address range entries in the list of address range entries into the allocated address space, wherein a first address range is associated with a pinned memory buffer that is mapped into a second address space allocated in a second GPU within the plurality of GPUs; and
adding the first process to the list of the set of processes, wherein the first process has access to any shared memory buffer corresponding to at least one of the address ranges mapped into the allocated address space.

11. The non-transitory computer-readable medium of claim 10 , wherein the list of the set of processes and the list of address range entries are red black tree data structures.

12. The non-transitory computer-readable medium of claim 10 , wherein the list of the set of processes and the list of address range entries are maintained in the system memory.

13. The non-transitory computer-readable medium of claim 10 , each of the shared memory buffers in the set of shared memory buffers is a page-locked memory buffer.

14. The non-transitory computer-readable medium of claim 10 , wherein the first GPU accesses any of the shared memory buffers in the set of shared memory buffers via a direct memory access operation.

15. The non-transitory computer-readable medium of claim 10 , wherein the processing unit further performs the step of receiving a request to create the first process in the first GPU from an application executing on the computer system.

16. The non-transitory computer-readable medium of claim 15 wherein the processing unit further performs the step of transmitting a notification to the application that the first process has been successfully created.

17. A computing system configured to create a first process that executes on a first graphics processing unit (GPU), the computer system comprising:
a system memory configured to store a set of shared memory buffers;
the plurality of GPUs; and
a processor coupled to the system memory, wherein the processor is configured perform the steps of:
maintaining a list of a set of processes executing on the plurality of GPUs,
maintaining a list of address range entries, wherein each address range entry in the list of address range entries comprises an address range corresponding to a different shared memory buffer in the set of shared memory buffers,
requesting that an address space be allocated in the first GPU for the first process,
requesting that the first GPU map the address range associated with each of the address range entries in the list of address range entries into the allocated address space, wherein a first address range is associated with a pinned memory buffer that is mapped into a second address space allocated in a second GPU within the plurality of GPUs, and
adding the first process to the list of the set of processes, wherein the first process has access to any shared memory buffer corresponding to at least one of the address ranges mapped into the allocated address space.

18. The computing system of claim 17 , wherein the list of the set of processes and the list of address range entries are stored in the system memory.

19. The computing system of claim 17 , wherein the system memory is further configured to store a page table including a locked page table entry for each shared memory buffer in the set of shared memory buffers, wherein the locked page table entry comprises a mapping of the shared memory buffer to a virtual address space of an application requesting allocation of the shared memory buffer.

20. The computing system of claim 17 , wherein the first GPU is configured to access any of the shared memory buffers in the set of shared memory buffers via a direct memory access operation.

21. The computing system of claim 20 , wherein the first GPU further comprises a GPU memory including a page table for mapping virtual addresses of the first process to physical addresses.

22. The computing system of claim 21 , wherein the first GPU adds a page table entry in the page table of the GPU memory to map each of shared memory buffers in the set of shared

Assignees

• Wilt Nicholas Patrick
• Nvidia Corp

Inventors

• Wilt Nicholas Patrick

Classifications

• G09G5/363

  Graphics controllers · CPC title

• G06F9/544 Primary

  Buffers; Shared memory; Pipes · CPC title

• G09G2370/02

  Networking aspects · CPC title

• G09G2360/08

  Power processing, i.e. workload management for processors involved in display operations, such as CPUs or GPUs · CPC title

• G09G2352/00

  Parallel handling of streams of display data · CPC title