Vertical memory control circuitry located in interconnect layers

Patent metadata

Field	Value
Publication number	US-10886286-B2
Application number	US-201816146938-A
Country	US
Kind code	B2
Filing date	Sep 28, 2018
Priority date	Sep 28, 2018
Publication date	Jan 5, 2021
Grant date	Jan 5, 2021

Abstract

An embodiment includes a substrate having a surface; a first layer that includes a metal and is on the substrate; a second layer that includes the metal and is on the first layer; a first switching device between the first and second layers; a second switching device between the first and second layers; a capacitor between the first and second layers, the capacitor including ferroelectric materials; a memory cell that includes the first switching device and the capacitor; an interconnect line that couples the first and second switching devices to each other; wherein: (a) the surface is substantially disposed in a first plane, and (b) a second plane is parallel to the first plane, the second plane intersecting the first and second switching devices. Other embodiments are addressed herein.

First claim

What is claimed is:

1. A system comprising:
a substrate having a surface;
a first layer that includes a metal, the first layer being on the substrate;
a second layer that includes the metal, the second layer being on the first layer;
a first switching device between the first and second layers, the first switching device comprising a first source region, a first channel region, and a first drain region;
a second switching device between the first and second layers, the second switching device comprising a second source region, a second channel region, and a second drain region;
a capacitor between the first and second layers, the capacitor including oxygen and at least one of hafnium, zirconium, barium, titanium, lead, or combinations thereof;
a memory cell that includes the first switching device and the capacitor;
an interconnect line that couples the first and second switching devices to each other;
wherein: (a) the surface is substantially disposed in a first plane, (b) a second plane is parallel to the first plane, the second plane intersecting the first and second switching devices; and (c) the second switching device is not included in any memory cell.

2. The system of claim 1 comprising a bit line, wherein the bit line is coupled to the interconnect line, the second switching device, and the memory cell.

3. The system of claim 2 wherein the bit line is between the first switching device and the substrate.

4. The system of claim 3 wherein the capacitor is between the first switching device and the second layer.

5. The system of claim 1 comprising a word line, wherein the word line is coupled to the interconnect line, the second switching device, and the memory cell.

6. The system of claim 5 , wherein the word line is between the first switching device and the second layer.

7. The system of claim 1 comprising a sense amplifier corresponding to the memory cell, wherein the sense amplifier includes the second switching device.

8. The system of claim 1 comprising a multiplexor (MUX), wherein:
the MUX includes the second switching device;
the MUX is to select one of the first switching device or a third switching device, the third switching device being included in an additional memory cell.

9. The system of claim 1 comprising:
an additional first switching device between the first switching device and the second layer, the additional first switching device comprising an additional first source region, an additional first channel region, and an additional first drain region;
an additional capacitor between the first switching device and the second layer, the additional capacitor including oxygen and at least one of hafnium, zirconium, barium, titanium, lead, or combinations thereof;
an additional memory cell that includes the additional first switching device and the additional capacitor;
an additional second switching device between the second switching device and the second layer, the additional second switching device comprising an additional second source region, an additional second channel region, and an additional second drain region;
wherein a third plane is parallel to the first plane, the third plane intersecting the additional first switching device and the additional second switching device;
wherein a first axis is orthogonal to the first plane, the first axis intersecting the first switching device and the additional first switching device;
wherein a second axis is orthogonal to the first plane, the second axis intersecting the second switching device and the additional second switching device.

10. The system of claim 9 comprising a multiplexor (MUX), wherein:
the MUX includes the second switching device;
the MUX is to select one of the first switching device or the additional first switching device.

11. The system of claim 1 comprising:
an integrated circuit on a first die;
a memory on a second die, the memory comprising the memory cell;
the first die and the second die both on a package substrate.

12. The system of claim 11 wherein the integrated circuit comprises a field programmable gate array (FPGA).

13. The system of claim 11 comprising:
a radiofrequency receiver; and
a chassis;
wherein the chassis includes the radiofrequency receiver and the package substrate.

14. The system of claim 1 , wherein:
an axis is orthogonal to the first plane;
the axis intersects the substrate, the first layer, the first switching device, and the second layer.

15. The system of claim 14 , wherein the axis intersects the first channel and at least one of the first source or the first drain.

16. The system of claim 1 wherein:
the first switching device is an NMOS transistor;
the second switching device is another NMOS transistor;
the first and second switching devices are included in a layer:
the layer does not include a PMOS transistor.

17. The system of claim 1 wherein:
the first switching device is a PMOS transistor;
the second switching device is another PMOS transistor;
the first and second switching devices are included in a layer:
the layer does not include an NMOS transistor.

18. The system of claim 1 comprising an additional component, wherein:
the additional component includes at least one of an additional capacitor or an additional switching device;
the memory cell includes the additional component.

19. The system of claim 1 comprising a bit line and a word line, wherein:
the second switching device is coupled to one of the bit line or the word line;
one of the word line or the bit line is between the first switching device and the substrate;
another of the word line or the bit line is between the first switching device and the second layer;
the word line and the bit line both couple to the memory cell.

20. The system of claim 1 wherein:
the first switching device includes a dielectric material;
the second switching device includes the dielectric material;
the first channel region includes a semiconductor material;
the second channel region includes the semiconductor material.

21. A system comprising:
a substrate having a surface;
a layer, including a metal, on the substrate;
a first switching device between the layer and the substrate, the first switching device comprising a first source region, a first channel region, and a first drain region;
a capacitor between the first switching device and the layer, the capacitor including a ferroelectric material;
a memory cell that includes the first switching device and the capacitor;
a second switching device between the layer and the substrate, the second switching device comprising a second source region, a second channel region, and a second drain region;
a bit line coupled to one of the first source region or the first drain region;
a word line coupled to the first gate region;
wherein the second switching device is not included in any memory cell.

22. The system of claim 21 wherein:
the second switching device is included in a multiplexor (MUX);
the surface is substantially disposed in a first plane;
a second plane is parallel to the first plane, the second plane intersecting the first and second switching devices.

23. The system of claim 21 wherein:
the ferroelectric material includes oxygen;
the ferroelectric material includes at least one of hafnium, zirconium, barium, titanium, lead, or combinations thereof.

24. A method comprising;
forming a first la

Assignees

• Intel Corp

Inventors

• Penumatcha Ashish Verma
• Morris Daniel H
• Avci Uygar E
• Young Ian A

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title