Multi-state device based on ion trapping

Patent metadata

Field	Value
Publication number	US-10886124-B2
Application number	US-201916725488-A
Country	US
Kind code	B2
Filing date	Dec 23, 2019
Priority date	Nov 30, 2017
Publication date	Jan 5, 2021
Grant date	Jan 5, 2021

Abstract

A semiconductor structure is provided that contains a non-volatile battery which controls gate bias and has increased output voltage retention and voltage resolution. The semiconductor structure may include a semiconductor substrate including at least one channel region that is positioned between source/drain regions. A gate dielectric material is located on the channel region of the semiconductor substrate. A battery stack is located on the gate dielectric material. The battery stack includes, a cathode current collector located on the gate dielectric material, a cathode material located on the cathode current collector, a first ion diffusion barrier material located on the cathode material, an electrolyte located on the first ion diffusion barrier material, a second ion diffusion barrier material located on the electrolyte, an anode region located on the second ion diffusion barrier material, and an anode current collector located on the anode region.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, the method comprising:
providing a material stack of a gate dielectric material and a battery stack on a surface of a semiconductor substrate, the battery stack comprising a cathode current collector located on the gate dielectric material, a cathode material located on the cathode current collector, a first ion diffusion barrier material located directly on the cathode material, an electrolyte located directly on the first ion diffusion barrier material, a second ion diffusion barrier material located directly on the electrolyte, and an anode current collector located atop the second ion diffusion barrier material; and
forming source/drain regions into the semiconductor substrate and on opposite sides of the material stack, wherein the forming of the source/drain regions is performed after the providing of the material stack.

2. The method of claim 1 , wherein the first and second ion diffusion barrier materials have a lithium diffusivity of less than 1E-6 cm 2 /s.

3. The method of claim 2 , wherein the lithium diffusivity of the first ion diffusion barrier material is from 1E-13 cm 2 /s to 1E-10 cm 2 /s, and the lithium diffusivity of the second ion diffusion barrier material is from 1E-12 cm 2 /s to 1E-7 cm 2 /s.

4. The method of claim 2 , wherein the first and second ion diffusion barrier materials comprise silicon dioxide, aluminum oxide, aluminum fluoride, magnesium oxide or a multilayered stack thereof.

5. The method of claim 1 , further comprising depositing an anode region on the second ion diffusion barrier material prior to forming the anode current collector.

6. The method of claim 1 , further comprising forming an anode region between the second ion diffusion barrier material and the anode current collector after the providing the material stack.

7. The method of claim 1 , wherein the gate dielectric material has sidewalls that are vertically aligned to sidewalls of the battery stack.

8. The method of claim 1 , further comprising forming a spacer along sidewalls of the material stack.

9. The method of claim 1 , wherein the second ion diffusion barrier material is composed of a compositionally same material as the first ion diffusion barrier material.

10. The method of claim 1 , wherein the second ion diffusion barrier material is composed of a compositionally different material than the first ion diffusion barrier material.

11. A method of forming a semiconductor structure, the method comprising:
providing a material stack of a gate dielectric material and a battery stack on a surface of a semiconductor substrate, the battery stack comprising a cathode current collector located on the gate dielectric material, a cathode material located on the cathode current collector, a first ion diffusion barrier material located directly on the cathode material, an electrolyte located directly on the first ion diffusion barrier material, a second ion diffusion barrier material located directly on the electrolyte, and an anode current collector located atop the second ion diffusion barrier material; and
forming source/drain regions into the semiconductor substrate and on opposite sides of the material stack, wherein the forming of the source/drain regions is performed prior to the providing of the material stack.

12. The method of claim 11 , wherein the source/drain regions are formed prior to forming the gate dielectric material of the material stack.

13. The method of claim 11 , wherein the first and second ion diffusion barrier materials have a lithium diffusivity of less than 1E-6 cm 2 /s.

14. The method of claim 13 , wherein the lithium diffusivity of the first ion diffusion barrier material is from 1E-13 cm 2 /s to 1E-10 cm 2 /s, and the lithium diffusivity of the second ion diffusion barrier material is from 1E-12 cm 2 /s to 1E-7 cm 2 /s.

15. The method of claim 13 , wherein the first and second ion diffusion barrier materials comprise silicon dioxide, aluminum oxide, aluminum fluoride, magnesium oxide or a multilayered stack thereof.

16. The method of claim 11 , further comprising depositing an anode region on the second ion diffusion barrier material prior to forming the anode current collector.

17. The method of claim 11 , further comprising forming an anode region between the second ion diffusion barrier material and the anode current collector after the providing the material stack.

18. The method of claim 11 , wherein the gate dielectric material has sidewalls that are vertically aligned to sidewalls of the battery stack.

19. The method of claim 11 , further comprising forming a spacer along sidewalls of the material stack.

20. The method of claim 11 , wherein the second ion diffusion barrier material is composed of a compositionally different material than the first ion diffusion barrier material.

Assignees

• IBM

Inventors

• Li Ning
• Lee Yun Seog
• De Souza Joel P
• Sadana Devendra K

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10P32/12

  between a solid phase and a gaseous phase · CPC title

• H10P32/174

  being Group III-V material · CPC title

• H10P32/14

  within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title