Systems and methods of fabricating semiconductor devices

Patent metadata

Field	Value
Publication number	US-10885261-B2
Application number	US-201916670282-A
Country	US
Kind code	B2
Filing date	Oct 31, 2019
Priority date	Oct 7, 2016
Publication date	Jan 5, 2021
Grant date	Jan 5, 2021

Abstract

Patterns in an integrated circuit may be evaluated, and a semiconductor device may be fabricated based on the evaluation. The evaluation may include a extracting and superimposing first patterns corresponding to design patterns of the same shape from input layout data generated based on inspecting the integrated circuit, generating distribution data of the first patterns based on the superimposed first patterns, determining an evaluation contour of the design patterns based on an evaluation condition and the distribution data, and generating output layout data based on replacing the first patterns with second patterns each having the evaluation contour. Weak points in the integrated circuit may be detected based on the output layout data. The fabricating may include selectively incorporating an integrated circuit into a semiconductor device based on a determination that the integrated circuit includes less than a threshold quantity and/or threshold concentration of weak points.

First claim

What is claimed is:

1. A method, performed by a computing system, of evaluating patterns of an integrated circuit, the method comprising:
obtaining input layout data generated based on inspecting the integrated circuit;
extracting and superimposing first patterns corresponding to design patterns having a common shape from the input layout data;
generating distribution data of the first patterns based on the superimposed first patterns;
determining an evaluation contour of the design patterns based on an evaluation condition and the distribution data;
generating output layout data based on replacing the first patterns with second patterns each having the evaluation contour; and
generating measurement data based on measuring at least one of the second patterns from the output layout data.

2. The method of claim 1 , further comprising:
obtaining coordinate data including coordinates of the first patterns;
wherein the extracting and superimposing the first patterns includes
generating contour images representing contours of the first patterns from the input layout data, based on the coordinates of the first patterns, and
generating a superimposed image based on superimposing the contour images.

3. The method of claim 2 , wherein the generating the contour images and the generating the superimposed image are performed in response to a determination that a quantity of first patterns is equal to or greater than a reference value.

4. The method of claim 1 , further comprising:
obtaining coordinate data including coordinates of the first patterns;
wherein the extracting and superimposing the first patterns includes
superimposing the first patterns so that the coordinates of the first patterns coincide with each other, and
extracting an overlap contour in which the first patterns are all superimposed.

5. The method of claim 4 , wherein the extracting the overlap contour is performed when a quantity of first patterns is equal to or less than a reference value.

6. The method of claim 1 , further comprising:
detecting a weak point of the integrated circuit based on design rule data of the integrated circuit and the measurement data.

7. A method, comprising:
obtaining input layout data generated based on inspecting an integrated circuit;
extracting and superimposing first patterns corresponding to design patterns having a common shape from the input layout data;
generating distribution data of the first patterns based on the superimposed first patterns;
determining an evaluation contour of the design patterns based on an evaluation condition and the distribution data;
generating output layout data based on replacing the first patterns with second patterns each having the evaluation contour;
determining whether the inspected integrated circuit includes at least a threshold quantity and/or threshold concentration of weak points based on measuring at least one of the second patterns from the output layout data; and
selectively incorporating the inspected integrated circuit into a semiconductor device based on a determination that the inspected integrated circuit includes less than the threshold quantity and/or the threshold concentration of weak points.

8. The method of claim 7 , further comprising:
obtaining coordinate data including coordinates of the first patterns;
wherein the extracting and superimposing the first patterns includes
generating contour images representing contours of the first patterns from the input layout data, based on the coordinates of the first patterns, and
generating a superimposed image based on superimposing the contour images.

9. The method of claim 8 , wherein the generating the contour images and the generating the superimposed image are performed in response to a determination that a quantity of first patterns is equal to or greater than a reference value.

10. The method of claim 7 , further comprising:
obtaining coordinate data including coordinates of the first patterns;
wherein the extracting and superimposing the first patterns includes
superimposing the first patterns so that the coordinates of the first patterns coincide with each other, and
extracting an overlap contour in which the first patterns are all superimposed.

11. The method of claim 10 , wherein the extracting the overlap contour is performed when a quantity of first patterns is equal to or less than a reference value.

12. The method of claim 7 , further comprising:
determining whether the inspected integrated circuit includes at least the threshold quantity and/or threshold concentration of weak points based on design rule data of the integrated circuit.

13. A method, comprising:
obtaining input layout data generated based on inspecting an integrated circuit;
extracting and superimposing first patterns corresponding to design patterns having a common shape from the input layout data;
determining an evaluation contour of the design patterns based on an evaluation condition and the superimposed first patterns;
determining whether the inspected integrated circuit includes at least a threshold quantity and/or threshold concentration of weak points based on replacing the first patterns with second patterns each having the evaluation contour and measuring at least one of the second patterns; and
selectively incorporating the inspected integrated circuit into a semiconductor device based on a determination that the inspected integrated circuit includes less than the threshold quantity and/or the threshold concentration of weak points.

14. The method of claim 13 , further comprising:
obtaining coordinate data including coordinates of the first patterns;
wherein the extracting and superimposing the first patterns includes
generating contour images representing contours of the first patterns from the input layout data, based on the coordinates of the first patterns, and
generating a superimposed image based on superimposing the contour images.

15. The method of claim 14 , wherein the generating the contour images and the generating the superimposed image are performed in response to a determination that a quantity of first patterns is equal to or greater than a reference value.

16. The method of claim 13 , further comprising:
obtaining coordinate data including coordinates of the first patterns;
wherein the extracting and superimposing the first patterns includes
superimposing the first patterns so that the coordinates of the first patterns coincide with each other, and
extracting an overlap contour in which the first patterns are all superimposed.

17. The method of claim 16 , wherein the extracting the overlap contour is performed when a quantity of first patterns is equal to or less than a reference value.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jong-Won
• Shin Jae-Pil
• Kim Tae-Heon
• Kim Yong-Hyeon
• Kim Tae-Hyun
• Park Jin-Kyu

Classifications

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title