Memory module with local synchronization and method of operation

Patent metadata

Field	Value
Publication number	US-10884923-B2
Application number	US-201916432700-A
Country	US
Kind code	B2
Filing date	Jun 5, 2019
Priority date	Jul 27, 2013
Publication date	Jan 5, 2021
Grant date	Jan 5, 2021

Abstract

A memory module-includes memory device groups, and a control circuit configurable to receive a system clock and input address and control (C/A) signals from a memory controller, and output a module clock, module C/A signals and data buffer control signals. The memory module further includes data buffers corresponding to respective memory device groups and configurable to receive the module clock and the data buffer control signals from the control circuit. A respective data buffer includes a n-bit wide data path and logic configured to control the data path in response to the data buffer control signals. The n-bit wide data path includes at least one programmable delay element controlled by the logic. The respective data buffer is further configurable to generate a respective local clock having a respective programmable delay from the module clock and to provide the respective local clock to a respective memory device group.

First claim

We claim:

1. A memory module configured to couple to a memory controller via one or more clock signal lines, a set of control signal lines and N sets of n-bit wide data/strobe signal lines, where N and n are integers larger than one, comprising:
a control circuit configured to receive a system clock from the memory controller via the one or more clock signal lines, and input address and control (C/A) signals from the memory controller via the control signal lines, the control circuit being further configured to output a module clock signal, module C/A signals and data buffer control signals in response to the system clock and the input C/A signals;
N data buffers configurable to receive the module clock signal and the data buffer control signals from the control circuit, wherein a respective data buffer of the N data buffers is configurable to operatively couple to a respective set of n-bit wide data/strobe signal lines, the respective data buffer including a n-bit wide data path and logic configured to control the data path in response to the data buffer control signals, the n-bit wide data path including at least one programmable delay element, wherein the respective data buffer is further configurable to generate a respective local clock signal in response to the module clock signal, and wherein the respective local clock signal is phase-locked with the module clock signal and has a respective programmable delay from the module clock signal; and
memory devices organized in one or more ranks and including N groups of memory devices corresponding to respective ones of the N data buffers, each group of memory devices including at least one memory device in each of the one or more ranks, wherein a respective group of the N groups of memory devices is configurable to receive the module C/A signals from the control circuit and a respective local clock signal from a corresponding data buffer of the N data buffers, and wherein the respective group of the N groups of memory devices is further configurable to communicate data and data strobe signals with the memory controller via the n-bit wide data path in the corresponding data buffer and in response to the module C/A signals from the control circuit and the respective local clock signal from the corresponding data buffer.

2. The memory module of claim 1 , wherein the control circuit, the N data buffers and the memory devices are coupled to a same printed circuit board, the printed circuit board including connectors formed along an edge thereof for connecting to respective ones of the one or more clock signal lines, the set of control signal lines and the N sets of data lines, and wherein the N data buffers are distributed along the edge of the printed circuit board and disposed between the N groups of memory devices and the edge connectors.

3. The memory module of claim 2 , wherein the respective data buffer includes a clock buffer to receive the module clock signal from the control circuit, a phase-locked loop circuit (PLL) to provide phase locking between the module clock signal and the respective local clock signal, a programmable delay circuit to delay the local clock signal by the programmable delay, and a clock driver to drive the local clock signal to a corresponding group of the memory devices.

4. The memory module of claim 3 , wherein the programmable delay circuit is controlled by the logic.

5. The memory module of claim 4 , wherein the respective data buffer includes one or more programmable registers programmable by the logic and configured to control the respective programmable delay.

6. The memory module of claim 5 , wherein the memory module is configurable to operate in at least a normal mode and a configuration mode, wherein the N data buffers are configured to buffer the data and data strobe signals between respective groups of memory devices and the memory controller during the normal mode, and wherein the respective data buffer is configured to program the one or more programmable registers during the configuration mode.

7. The memory module of claim 1 , wherein the respective data buffer includes one or more programmable registers programmable by the logic and configured to control the respective programmable delay.

8. The memory module of claim 7 , wherein the memory module is configurable to operate in at least a normal mode and a configuration mode, wherein the N data buffers are configured to buffer the data and data strobe signals between respective groups of memory devices and the memory controller during the normal mode, and wherein the respective data buffer is configured to program the one or more programmable registers during the configuration mode.

9. The memory module of claim 1 , wherein the respective data buffer includes one or more programmable registers configurable by the logic to time the data and data strobes being communicated via the respective data buffer.

10. The memory module of claim 9 , wherein the respective data buffer is configured to program the one or more registers according to signals output from the control circuit during the configuration mode.

11. The memory module of claim 9 , wherein the control circuit does not transmit any clock signals to the memory devices.

12. The memory module of claim 9 , wherein the data buffer control signals are different from the module C/A signals.

13. The memory module of claim 9 , wherein the memory devices are organized in one or more ranks and are each n-bit or n/2—bit wide, and wherein each group of memory devices include at least one memory device from each of the one or more ranks.

14. The memory module of claim 13 , wherein each of the memory devices is n-bits wide.

15. The memory module of claim 13 , wherein each of the memory devices is n/2 bits wide.

16. A method of operating a memory module couple to a memory controller via one or more clock signal lines, a set of control signal lines and N sets of n-bit wide data/strobe signal lines, where N and n are integers larger than one, the memory module including memory devices organized in one or more ranks, the memory devices including N groups of memory devices corresponding to respective sets of the N sets of n-bit wide data/strobe signal lines, each group of memory devices including at least one memory device in each of the one or more ranks, the method comprising:
receiving a system clock from the memory controller via the one or more clock signal lines, and input address and control (C/A) signals from the memory controller via the control signal lines;
outputting a module clock signal, module C/A signals and data buffer control signals in response to the system clock and the input C/A signals;
controlling N data paths in response to the data buffer control signals, each respective data path of the N data paths being n-bit wide and coupled between a respective set of n-bit wide data/strobe signal lines and a respective group of memory devices, wherein controlling the each respective data path include controlling at least one respective programmable delay element;
generating N local clock signals in response to the module clock signal, each respective local clock signal of the N local clock signals being phase-locked with the module clock signal and having a respective programmable delay from the module clock signal;
outputting the N local clock signals to respective groups of N groups of memory devices; and
performing memory read or write operations at a selected rank of the memory devices in response to the module C/A signals and the N local clock signals to communicate data and data strobe signals with the memory

Assignees

• Netlist Inc

Inventors

• Lee Hyun
• Bhakta Jayesh R

Classifications

• G11C5/04 Primary

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C7/1093

  Input synchronization · CPC title

• G11C7/1066

  Output synchronization · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title