Integrated circuit device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10879398-B2
Application number	US-201816111643-A
Country	US
Kind code	B2
Filing date	Aug 24, 2018
Priority date	Jan 18, 2018
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

An integrated circuit device includes a device isolation trench defining an active area, a gate trench extending in a first direction across the active area and the device isolation film, a gate dielectric film covering an inner wall of the gate trench, and a conductive line filling a part of the gate trench above the gate dielectric film. The active area includes a fin body portion located under the conductive line, and a thinner fin portion protruding from the fin body portion toward the conductive line and having a width less than a width of the fin body portion in the first direction.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a substrate having a device isolation trench that defines an active area;
a device isolation film filling the device isolation trench around the active area;
a gate trench extending in a first direction across the active area and the device isolation film;
a gate dielectric film covering an inner wall of the gate trench; and
a conductive line filling a part of the gate trench above the gate dielectric film,
wherein the active area comprises a fin body portion under the conductive line, a thinner fin portion protruding from the fin body portion toward the conductive line and having a first width less than a second width of the fin body portion in the first direction, an upper active area having an uppermost surface at a level higher than a top surface of the conductive line, and a middle active area connected between the fin body portion and the upper active area and having a third width less than the second width of the fin body portion and less than a fourth width of the upper active area in a horizontal direction.

2. The integrated circuit device of claim 1 , wherein the gate trench comprises a first bottom where the device isolation film is exposed and a second bottom where the thinner fin portion and the fin body portion are exposed, and
the first bottom is at a level lower than the second bottom.

3. The integrated circuit device of claim 1 , wherein the conductive line comprises a recess bottom that surrounds the thinner fin portion.

4. The integrated circuit device of claim 1 , wherein the active area has a side wall including a lateral recess at a same level as the thinner fin portion, and
the device isolation film has a side wall including a laterally protruding insulation portion that protrudes toward the lateral recess.

5. The integrated circuit device of claim 1 , wherein a lateral recess extending long in a horizontal direction is formed in a side wall of the active area.

6. The integrated circuit device of claim 1 , wherein the middle active area and the thinner fin portion are at a same level in the horizontal direction.

7. The integrated circuit device of claim 1 , wherein a side wall of the device isolation film includes a portion having a negative profile extending such that a width of the device isolation film in a horizontal direction decreases toward an uppermost surface of the active area.

8. The integrated circuit device of claim 1 , wherein a lateral recess extending in the horizontal direction is formed in a side wall of the active area, and the device isolation film has a side wall including a laterally protruding insulation portion that protrudes toward the lateral recess, and
wherein the device isolation film comprises a gap-fill insulating film and an insulating liner that surrounds the gap-fill insulating film,
the insulating liner comprising a protruding portion that protrudes toward the laterally protruding insulation portion.

9. An integrated circuit device comprising:
a substrate having a plurality of active areas that are arranged in a row in a first direction;
a device isolation film surrounding the plurality of active areas on the substrate; and
a conductive line extending across the plurality of active areas in the substrate,
wherein each of the plurality of active areas comprises a fin body portion under the conductive line, a thinner fin portion protruding from the fin body portion toward the conductive line and having a first width less than a second width of the fin body portion in the first direction, an upper active area having an uppermost surface at a level higher than a top surface of the conductive line, and a middle active area arranged between the upper active area and the fin body portion and having a third width less than the second width of the fin body portion and less than a fourth width of the upper active area in the first direction.

10. The integrated circuit device of claim 9 , wherein each of the plurality of active areas includes a gate trench that accommodates the conductive line, and
the gate trench has a bottom that is defined by a surface of the thinner fin portion and an upper surface of the fin body portion.

11. The integrated circuit device of claim 9 , wherein the device isolation film includes a gate trench that accommodates the conductive line, and
the gate trench has a bottom at a level lower than a level of the thinner fin portion.

12. The integrated circuit device of claim 9 , wherein a lateral recess extending long in a horizontal direction is formed in a side wall of each of the plurality of active areas.

13. The integrated circuit device of claim 12 , wherein the device isolation film includes a laterally protruding insulation portion that protrudes toward the lateral recess.

14. An integrated circuit device comprising:
a substrate having a cell array area, a peripheral circuit area, and an interface area between the cell array area and the peripheral circuit area;
a plurality of active areas in the substrate in the cell array area;
a device isolation film covering a side wall of each of the plurality of active areas in the cell array area;
an interface device isolation film filling an interface trench formed in the substrate in the interface area; and
a plurality of conductive lines extending in the cell array area across the plurality of active areas in a first direction,
wherein each of the plurality of active areas comprises a fin body portion located under the conductive line, a thinner fin portion protruding from the fin body portion toward the conductive line and having a first width less than a second width of the fin body portion in the first direction, an upper active area having an uppermost surface at a level higher than a top surface of the plurality of conductive lines, and a middle active area connected between the fin body portion and the upper active area and having a third width less than the second width of the fin body portion and less than a fourth width of the upper active area in the first direction.

15. The integrated circuit device of claim 14 , wherein the conductive line comprises a first portion facing the thinner fin portion, a second portion facing an upper surface of the fin body portion, and a third portion facing the device isolation film.

16. The integrated circuit device of claim 14 , wherein each of the plurality of active areas has a side wall in which a lateral recess is formed, the lateral recess extending long in a horizontal direction at a same level as a level of the thinner fin portion.

17. The integrated circuit device of claim 14 , wherein the device isolation film has a side wall on which a laterally protruding insulation portion is located, the laterally protruding insulation portion extending long in a horizontal direction at a same level as a level of the thinner fin portion.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Ji-Seung
• Kang Yun-Seung
• Lee Soung-Hee
• Chung Sang-Gyo
• Lee Hyun-Chul

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014 Primary

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10B12/34

  the transistor being at least partially in a trench in the substrate · CPC title

• H10B12/30 Primary

  DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells · CPC title

• H10B12/09

  with simultaneous manufacture of the peripheral circuit region and memory cells · CPC title