Semiconductor structure with shallow trench isolation and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9646871-B2
Application number	US-201414337562-A
Country	US
Kind code	B2
Filing date	Jul 22, 2014
Priority date	Jul 22, 2014
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A semiconductor structure includes a semiconductor substrate and a shallow trench isolation (STI). The STI includes a sidewall interfacing with the semiconductor substrate. The STI extrudes from a bottom portion of the semiconductor substrate, and the STI includes a bottom surface contacting the bottom portion of the semiconductor substrate; a top surface opposite to the bottom surface. The bottom surface includes a width greater than a width of the top surface.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a semiconductor substrate comprising a fin structure; and
a shallow trench isolation (STI) including a sidewall interfacing with the fin structure, the fin structure further comprising:
a top surface including a width, wherein the top surface is higher than the top surface of the STI;
a bottom width at a horizontal level of a bottom portion of the semiconductor substrate;
a first turning point and a second turning point, wherein the width of the top surface is greater than the bottom width, the first turning point meets with a top surface of the STI, and a sidewall of the fin structure is tapered from the first turning point to the second turning point; and
a third turning point between the second turning point and the bottom portion of the semiconductor substrate, the fin structure at the third turning point comprising a width greater than the bottom width.

2. The semiconductor structure of claim 1 , wherein the fin structure comprises a minimal width at the second turning point.

3. The semiconductor structure of claim 1 , wherein the STI comprises:
a bottom surface contacting the bottom portion of the semiconductor substrate; and
a top surface opposite to the bottom surface,
wherein the bottom surface comprises a width greater than a width of the top surface.

4. The semiconductor structure of claim 3 , wherein the STI has a width at the second turning point equal to or greater than the width of the bottom surface of the STI.

5. The semiconductor structure of claim 1 , wherein the STI has a width at the third turning point equal to or greater than the width of the top surface of the STI.

6. The semiconductor structure of claim 1 , wherein the fin structure comprises different widths at the second turning point and the third turning point.

7. The semiconductor structure of claim 1 , wherein the sidewall of the fin structure is tapered from the third turning point to the second turning point.

8. The semiconductor structure of claim 1 , wherein the fin structure comprises a constant width between the top surface of the fin structure and the first turning point.

9. The semiconductor structure of claim 1 , further comprising a gate structure over the fin structure and the STI.

10. The semiconductor structure of claim 9 , wherein the gate structure comprises a gate dielectric layer over the top surfaces of the fin structure and the STI.

11. The semiconductor structure of claim 10 , wherein the gate structure further comprises a gate electrode over the gate dielectric layer.

12. The semiconductor structure of claim 1 , further comprising a second shallow trench isolation (STI) including a sidewall interfacing with the fin structure, wherein the second STI comprises:
a bottom surface contacting the bottom portion of the semiconductor substrate; and
a top surface opposite to the bottom surface of the second STI,
wherein the bottom surface comprises a width greater than a width of the top surface of the second STI.

13. The semiconductor structure of claim 12 , wherein the STI and the second STI are arranged in a fine-pitch region and a coarse-pitch region, respectively, and the pitch in the fine-pitch region is smaller than that of in the coarse-pitch region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Che-Cheng
• Cheng Tung-Wen
• Hseih Jui Fu
• Lin Mu-Tsang

Classifications

• H10W10/0145

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

• H10W10/0147

  the shapes being altered by a local oxidation of silicon process, e.g. trench corner rounding by LOCOS · CPC title

• H10W10/17 Primary

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L21/76232

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic