Techniques for pre-processing index buffers for a graphics processing pipeline

US10878611B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10878611-B2
Application numberUS-201815881572-A
CountryUS
Kind codeB2
Filing dateJan 26, 2018
Priority dateJan 26, 2018
Publication dateDec 29, 2020
Grant dateDec 29, 2020

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  1. Title

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  5. First independent claim

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Abstract

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In various embodiments, a deduplication application pre-processes index buffers for a graphics processing pipeline that generates rendered images via a shading program. In operation, the deduplication application causes execution threads to identify a set of unique vertices specified in an index buffer based on an instruction. The deduplication application then generates a vertex buffer and an indirect index buffer based on the set of unique vertices. The vertex buffer and the indirect index buffer are associated with a portion of an input mesh. The graphics processing pipeline then renders a first frame and a second frame based on the vertex buffer, the indirect index buffer, and the shading program. Advantageously, the graphics processing pipeline may re-use the vertex buffer and indirect index buffer until the topology of the input mesh changes.

First claim

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What is claimed is: 1. A computer-implemented method for pre-processing index buffers for a graphics processing pipeline, the method comprising: causing a first plurality of execution threads to identify a first plurality of unique vertices specified in a first index buffer based on a first instruction; generating a first vertex buffer based on the first plurality of unique vertices, wherein the first vertex buffer is associated with a first portion of an input mesh; generating a first indirect index buffer based on the first plurality of unique vertices, wherein the first indirect index buffer is associated with the first portion of the input mesh; rendering a first frame using a first set of identifiers stored in the first vertex buffer, the first indirect index buffer, and a shading program; determining that a topology associated with the input mesh has not changed between the first frame and a second frame; and in response to determining that the topology has not changed, rendering the second frame using the first set of identifiers stored in the first vertex buffer, the first indirect index buffer, and the shading program. 2. The method of claim 1 , wherein generating the first vertex buffer comprises aggregating the first plurality of unique vertices and a second plurality of unique vertices also specified in the first index buffer. 3. The method of claim 2 , further comprising causing a second plurality of execution threads to identify the second plurality of unique vertices specified in the first index buffer based on the first instruction. 4. The method of claim 1 , wherein generating the first vertex buffer comprises: determining that a number of vertices included in the first plurality of unique vertices is greater than a maximum number of vertices per batch; and partitioning the first plurality of unique vertices between the first vertex buffer and a second vertex buffer. 5. The method of claim 1 , wherein identifying the first plurality of unique vertices comprises: for each execution thread included in the first plurality of execution threads, loading a vertex specified in the first index buffer; causing the first plurality of execution threads to execute the first instruction and generate a plurality of match masks; and performing one or more comparison operations on the plurality of match masks. 6. The method of claim 5 , wherein generating the first indirect index buffer comprises mapping a first execution thread included in the first plurality of execution threads to a first vertex included in the first plurality of unique vertices based on a first match mask included in the plurality of match masks. 7. The method of claim 1 , wherein identifying the first plurality of unique vertices comprises: causing the first plurality of execution threads to execute the first instruction on a first plurality of vertices specified in the first index buffer to identify a first unique vertex included in the first plurality of vertices and a first duplicate vertex included in the first plurality of vertices; selecting a second plurality of vertices specified in the first index buffer, wherein the second plurality of vertices includes the first unique vertex but does not include the first duplicate vertex; and causing the first plurality of execution threads to execute the first instruction on the second plurality of vertices to identify at least one vertex in the first plurality of unique vertices. 8. The method of claim 7 , further comprising: prior to causing the first plurality of execution threads to execute the first instruction on the first plurality of vertices, configuring the first instruction to perform exhaustive comparison operations between the first plurality of vertices; and prior to causing the first plurality of execution threads to execute the first instruction on the second plurality of vertices, configuring the first instruction to perform non-exhaustive comparison operations between the second plurality of vertices. 9. The method of claim 1 , further comprising: determining that the topology associated with the input mesh has changed between the second frame and a third frame; in response to determining that the topology has changed: causing a second plurality of execution threads to identify a second plurality of unique vertices specified in a second index buffer associated with the input mesh based on the first instruction, and generating a second vertex buffer and a second indirect index buffer based on the second plurality of unique vertices, wherein the graphics processing pipeline renders the third frame based on the second vertex buffer, the second indirect index buffer, and the shading program. 10. One or more non-transitory computer-readable storage media including instructions that, when executed by one or more processors, cause the one or more processors to pre-process index buffers for a graphics processing pipeline by performing the steps of: causing a first plurality of execution threads to identify a first plurality of unique vertices specified in a first index buffer based on a first instruction that performs one or more comparison operations between the first plurality of execution threads; generating a first vertex buffer based on the first plurality of unique vertices; generating a first indirect index buffer based on the first plurality of unique vertices; rendering a first frame using a first set of identifiers stored in the first vertex buffer, the first indirect index buffer, and a shading program determining that a topology associated with the input mesh has not changed between the first frame and a second frame; and in response to determining that the topology has not changed, rendering the second frame using the first set of identifiers stored in the first vertex buffer, the first indirect index buffer, and the shading program. 11. The one or more non-transitory computer-readable storage media of claim 10 , wherein generating the first vertex buffer comprises aggregating the first plurality of unique vertices and a second plurality of unique vertices also specified in the first index buffer. 12. The one or more non-transitory computer-readable storage media of claim 10 , wherein generating the first vertex buffer comprises: determining that a number of vertices included in the first plurality of unique vertices is greater than a maximum number of vertices per batch; and partitioning the first plurality of unique vertices between the first vertex buffer and a second vertex buffer. 13. The one or more non-transitory computer-readable storage media of claim 10 , wherein identifying the first plurality of unique vertices comprises: for each execution thread included in the first plurality of execution threads, loading a vertex specified in the first index buffer; causing the first plurality of execution threads to execute the first instruction and generate a plurality of match masks; and performing one or more comparison operations on the plurality of match masks. 14. The one or more non-transitory computer-readable storage media of claim 10 , wherein identifying the first plurality of unique vertices comprises: causing the first plurality of execution threads to execute the first instruction on a first plurality of vertices specified in the first index buffer to identify a first unique vertex included in the first plurality of vertices and a first duplicate vertex included in the first plurality of vertices; selecting a second plurality of vertices specified in the first index buffer, wherein the second plurality of vertices includes the first uni

Assignees

Inventors

Classifications

  • Finite element generation, e.g. wire-frame surface description, {tesselation} · CPC title

  • G06T15/005Primary

    General purpose rendering architectures · CPC title

  • Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

  • Shading · CPC title

  • Constructive solid geometry [CSG] using solid primitives, e.g. cylinders, cubes · CPC title

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What does patent US10878611B2 cover?
In various embodiments, a deduplication application pre-processes index buffers for a graphics processing pipeline that generates rendered images via a shading program. In operation, the deduplication application causes execution threads to identify a set of unique vertices specified in an index buffer based on an instruction. The deduplication application then generates a vertex buffer and an …
Who is the assignee on this patent?
Nvidia Corp
What technology area does this patent fall under?
Primary CPC classification G06T15/005. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 29 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 10 related publications on this page (citations in our corpus or others sharing the same primary CPC).