Coherence-based attack detection
US-12147528-B2 · Nov 19, 2024 · US
US2015113224A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2015113224-A1 |
| Application number | US-201414163913-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jan 24, 2014 |
| Priority date | Oct 23, 2013 |
| Publication date | Apr 23, 2015 |
| Grant date | — |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
Atomic write operations for storage devices are implemented by maintaining the data that would be overwritten in the cache until the write operation completes. After the write operation completes, including generating any related metadata, a checkpoint is created. After the checkpoint is created, the old data is discarded and the new data becomes the current data for the affected storage locations. If an interruption occurs prior to the creation of the checkpoint, the old data is recovered and any new is discarded. If an interruption occurs after the creation of the checkpoint, any remaining old data is discarded and the new data becomes the current data. Write logs that indicate the locations affected by in progress write operation are used in some implementations. If neither all of the new data nor all of the old data is recoverable, a predetermined pattern can be written into the affected locations.
Opening claim text (preview).
What is claimed is: 1 . A method comprising: after receiving, at a storage controller, an indication of a write command that indicates a target location in storage associated with the storage controller and writing data of the write command into a first plurality of cache blocks of cache of the storage controller, determining a second plurality of cache blocks of the cache that correspond to storage locations to which the first plurality of cache blocks also correspond; for each of the second plurality of cache blocks, preserving a reference to the cache block and indicating that data hosted in the cache block was stored in the cache block prior to receiving the write command; for each of the first plurality of cache blocks, storing a reference to the cache block and indicating that data hosted in the cache block correspond to the write command; and after preserving the references to the second plurality of blocks and indicating that the data hosted in the second plurality of cache blocks precede the write command and after storing the references to the first plurality of cache blocks and indicating that the data hosted in the first plurality of cache blocks correspond to the write command, storing information that indicates the write command has been completed. 2 . The method of claim 1 further comprising, for each of the second plurality of cache blocks, indicating that the data hosted in the cache block is invalid after said storing information that indicates the write command has been completed. 3 . The method of claim 2 further comprising, for each of the first plurality of cache blocks, clearing the indications that the data hosted in the cache block correspond to the write command, after data hosted in the second plurality of cache blocks have been indicated as invalid. 4 . The method of claim 3 further comprising clearing the information that was stored to indicate completion of the write command, after said clearing the indications that the data hosted in the first plurality of cache blocks correspond to the write command. 5 . The method of claim 1 , wherein said determining the second plurality of cache blocks that correspond to storage locations to which the first plurality of cache blocks also correspond comprises: determining index values based, at least in part, on indications of the storage locations; and accessing a structure with the index values, wherein each of the index values indexes an entry in the structure that indicates a different one of the second plurality of cache blocks. 6 . The method of claim 5 , wherein said preserving the reference to the cache block for each of the second plurality of cache blocks comprises storing the references to the second plurality of cache blocks in a second structure; and wherein said storing the references to the first plurality of cache blocks comprises storing each of the references to the first plurality of cache blocks into the structure with the index values. 7 . The method of claim 1 further comprising: after recovering from an adverse event, determining existence of the information that indicates the write command has been completed; determining that the first and the second pluralities of cache blocks correspond to the information that indicates the write command has been completed; for each of the second plurality of cache blocks, indicating that the data hosted in the cache block is invalid; for each of the first plurality of cache blocks, clearing the indications that the data hosted in the cache block correspond to the write command; and removing the information that indicates the write command has been completed. 8 . The method of claim 1 further comprising: after recovering from an adverse event, determining a reference to a third cache block of the cache that does not correspond to the information that indicates the write command has been completed; determining whether the data hosted in the third cache block is indicated as preceding a write command or corresponding to a write command; and indicating the data hosted in the third cache block as invalid if the data hosted in the third cache block is indicated as corresponding to a write command. 9 . The method of claim 1 , further comprising: determining that mirroring to an alternate storage controller is enabled; communicating, to the alternate controller, the first plurality of cache blocks, the indications that the data hosted in the first plurality of cache blocks correspond to the write command, the second plurality of cache blocks, and the indications that the data hosted in the second plurality; communicating, to the alternate controller, the information that indicates the write command has completed; and in response to the alternate controller acknowledging receipt of the communicated information, indicating that mirroring is complete. 10 . One or more computer readable storage media having program code encoded therein, the program code comprising program code to: record indications of addressable units of a cache to which data of a write command has been written; determine whether other addressable units of the cache are already indicated for storage locations that correspond to the write command; indicate that the other addressable units of the cache represent a state of a subset of the cache in which the write command is not performed, wherein the subset of the cache corresponds to the addressable units and the other addressable units; indicate that the addressable units of the cache represent a state of the subset of the cache in which the write command completes; store data that indicates the write command for a machine that supplied the write command has completed after the addressable units of the cache are indicated as representing a state of the subset of the cache in which the write command completes and after the other addressable units of the cache are indicated as representing a state of the subset of the cache in which the write command is not performed; after recovery from an adverse event, indicate data hosted in the other addressable units of the cache as invalid if the data that indicate the write command for the machine that supplied the write command does not indicate that the write command was completed; and after recovery from an adverse event, indicate data hosted in the addressable units of the cache as invalid if the data that indicate the write command for the machine that supplied the write command does not indicate that the write command was completed. 11 . The computer readable storage medium of claim 10 further comprising program code to: determine whether mirroring to an alternate controller is enabled; if mirroring is enabled, communicate, to the alternate controller, that the addressable units of the cache are indicated as representing a state of the subset of the cache in which the write command completes; then communicate, to the alternate controller, that the other addressable units of the cache are indicated as representing a state of the subset of the cache in which the write command is not performed; then communicate, to the alternate controller, the data that indicates the write command was completed for the machine that supplied the write command; and indicate that mirroring is complete after receipt of acknowledgement of the communications from the alternate controller. 12 . The computer readable storage medium of claim 10 , wherein the program code to determine whether other addressable units of the cache are already indicated for storage locations that correspond to the write command comprise program code to: determine indexes bas
involving logging of persistent data for recovery · CPC title
Mapping of cache memory to specific storage devices or parts thereof · CPC title
Cache consistency protocols · CPC title
using clearing, invalidating or resetting means · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.