Deskewing method for a physical layer interface on a multi-chip module

Patent metadata

Field	Value
Publication number	US-10873445-B2
Application number	US-201916709472-A
Country	US
Kind code	B2
Filing date	Dec 10, 2019
Priority date	Apr 29, 2019
Publication date	Dec 22, 2020
Grant date	Dec 22, 2020

Abstract

Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

First claim

What is claimed is:

1. A circuit comprising:
first circuitry configured to sample a first local clock with a first global clock;
second circuitry configured to generate phase-shifted versions of the first local clock in single unit interval step sizes; and
control logic configured to:
perform a sweep of phases of the first local dock in single unit interval step sizes until an edge transition of the first global clock is detected;
adjust a phase of the first local dock to meet setup and hold timing requirements for sampling a first data signal on a first lane of a plurality of lanes of a communication channel, responsive to detecting said edge transition; and
sample the first data signal using a phase-adjusted first local clock to generate a first data sequence.

2. The circuit as recited in claim 1 , wherein the first circuitry comprises a first register configured to sample the first local clock with the first global clock, wherein the first global clock is coupled to a clock port of the first register.

3. The circuit as recited in claim 2 , wherein the second circuitry comprises a first barrel shifter configured to generate phase-shifted versions of the first local clock in single unit interval step sizes.

4. The circuit as recited in claim 3 , further comprising:
a second register configured to sample a second local clock with a second global clock;
a second barrel shifter configured to generate phase-shifted versions of the second local clock in single unit interval step sizes;
wherein the control logic is further configured to:
perform a sweep of phases of the second local clock in single unit interval step sizes until a given edge transition of the second global clock is detected;
adjust a phase of the second local clock to meet setup and hold timing requirements for sampling a second data signal on a second lane of the plurality of lanes of the communication channel, responsive to detecting the given edge transition; and
add one or more unit intervals of delay to the second local clock to align the second local clock with the first local clock.

5. The circuit as recited in claim 4 , wherein the control logic is further configured to sample the second data signal using a delayed version of the phase-adjusted second local clock to generate a second data sequence.

6. The circuit as recited in claim 1 , wherein the first local clock has a same frequency as the first global clock, and wherein the control logic is configured to convey the first data sequence to a serializer.

7. The circuit as recited in claim 1 , further comprising a finite state machine configured to determine, across multiple edge transitions, an average phase adjustment to apply to the first local clock.

8. A method comprising:
sampling, with first circuitry, a first local clock with a first global clock;
generating, with second circuitry, phase-shifted versions of the first local clock in single unit interval step sizes;
performing, with control logic, a sweep of phases of the first local clock in single unit interval step sizes until an edge transition of the first global clock is detected;
adjusting a phase of the first local clock to meet setup and hold timing requirements for sampling a first data signal on a first lane of a plurality of lanes of a communication channel, responsive to detecting said edge transition; and
sampling the first data signal using a phase-adjusted first local clock to generate a first data sequence.

9. The method as recited in claim 8 , wherein the first circuitry comprises a first register configured to sample the first local clock with the first global clock, wherein the first global clock is coupled to a clock port of the first register.

10. The method as recited in claim 9 , wherein the second circuitry comprises a first barrel shifter configured to generate phase-shifted versions of the first local clock in single unit interval step sizes.

11. The method as recited in claim 10 , further comprising:
sampling, with a second register, a second local clock with a second global clock;
generating, with a second barrel shifter, phase-shifted versions of the second local clock in single unit interval step sizes;
performing, with the control logic, a sweep of phases of the second local clock in single unit interval step sizes until a given edge transition of the second global clock is detected;
adjusting a phase of the second local dock to meet setup and hold timing requirements for sampling a second data signal on a second lane of the plurality of lanes of the communication channel, responsive to detecting the given edge transition; and
adding one or more unit intervals of delay to the second local clock to align the second local clock with the first local clock.

12. The method as recited in claim 11 , further comprising sampling the second data signal using a delayed version of the phase-adjusted second local clock to generate a second data sequence.

13. The method as recited in claim 8 , further comprising conveying the first data sequence to a serializer, wherein the first local clock has a same frequency as the first global clock.

14. The method as recited in claim 8 , further comprising determining, across multiple edge transitions, an average phase adjustment to apply to the first local clock.

15. A system comprising:
a first functional unit;
a channel with a plurality of communication lanes;
a second functional unit coupled to the first functional unit via the channel,
wherein the second functional unit conveys at least a first global clock and
a first data signal to the first functional unit via a first lane of the channel;

wherein the first functional unit is configured to:
sample, with first circuitry, a first local clock with the first global clock;
generate, with second circuitry, phase-shifted versions of the first local clock in single unit interval step sizes;
perform, with control logic, a sweep of phases of the first local clock rn single unit interval step sizes until an edge transition of the first global clock is detected;
adjust a phase of the first local clock to meet setup and hold timing requirements for sampling the first data signal, responsive to detecting said edge transition; and
sample the first data signal using a phase-adjusted first local clock to generate a first data sequence.

16. The system as recited in claim 15 , wherein the first circuitry comprises a first register configured to sample the first local clock with the first global clock, wherein the first global clock is coupled to a clock port of the first register.

17. The system as recited in claim 16 , wherein the second circuitry comprises a first barrel shifter configured to generate phase-shifted versions of the first local dock in single unit interval step sizes.

18. The system as recited in claim 17 , wherein the first functional unit is further configured to:
sample, with a second register, a second local clock with a second global clock;
generate, with a second barrel shifter, phase-shifted versions of the second local clock in single unit interval step sizes;
wherein the control logic is further configured to:
perform, with control logic, a sweep of phases of the second local clock in single unit interval step sizes until a given edge transition of the second global clock is detected;
adjust a phase of the second local clock to meet setup and hold timing requirements for sampling a second data signal on a second lane of the plurality of lanes of the communication channel, responsive to detecting the given e

Assignees

• Advanced Micro Devices Inc
• Ati Technologies Ulc

Inventors

• Gupta Varun
• Paraschou Milam
• Talbot Gerald R
• Dollin Gurunath
• Tohidi Damon
• Carpenter Eric Ian
• Gallun Chad S
• Cooper Jeffrey
• Cho Hanwoo
• Likens Iii Thomas H
• Dow Scott F
• Tresidder Michael J

Classifications

• H04L25/14 Primary

  Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver} · CPC title

• H04L7/04 Primary

  Speed or phase control by synchronisation signals {(H04L7/0075 takes precedence)} · CPC title

• H04L7/0337 Primary

  Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals · CPC title

• H04L7/0008

  Synchronisation information channels, e.g. clock distribution lines · CPC title