Substrate resistor and method of making same

Patent metadata

Field	Value
Publication number	US-10872963-B2
Application number	US-201916416465-A
Country	US
Kind code	B2
Filing date	May 20, 2019
Priority date	Jun 26, 2012
Publication date	Dec 22, 2020
Grant date	Dec 22, 2020

Abstract

A semiconductor structure can include a resistor on a substrate formed simultaneously with other devices, such as transistors. A diffusion barrier layer formed on a substrate is patterned to form a resistor and barrier layers under a transistor gate. A filler material, a first connector, and a second connector are formed on the resistor at the same manner and time as the gate of the transistor. The filler material is removed to form a resistor on a substrate.

First claim

What is claimed is:

1. A semiconductor structure comprising:
an isolation region in a substrate;
a resistor over the isolation region;
a first connector in contact with the resistor;
a second connector in contact with the resistor, the second connector being laterally spaced apart from the first connector; and
a semiconductor material layer in direct contact with the resistor, wherein the semiconductor material layer is interposed between the first connector and the second connector, and wherein a topmost surface of the semiconductor material layer is below a topmost surface of the first connector and a topmost surface of the second connector.

2. The semiconductor structure of claim 1 , further comprising an etch stop layer lining a first sidewall of the first connector, wherein the etch stop layer is in physical contact with the resistor.

3. The semiconductor structure of claim 2 , further comprising a spacer on a second sidewall of the first connector, wherein the second sidewall of the first connector is opposite to the first sidewall of the first connector, and wherein the spacer is in physical contact with the resistor.

4. The semiconductor structure of claim 3 , wherein the spacer is in physical contact with the isolation region.

5. The semiconductor structure of claim 1 , further comprising a dielectric layer over the semiconductor material layer, wherein the dielectric layer is interposed between the first connector and the second connector.

6. The semiconductor structure of claim 1 , wherein a width of the resistor is greater than a width of the semiconductor material layer.

7. The semiconductor structure of claim 1 , wherein a sidewall of the resistor is aligned with a sidewall of the first connector.

8. A semiconductor structure comprising:
an isolation region embedded in a substrate;
a resistor over the isolation region;
a first connector contacting the resistor;
a second connector contacting the resistor;
an etch stop layer lining a first sidewall of the first connector and a first sidewall of the second connector, the first sidewall of the first connector facing the first sidewall of the second connector; and
a semiconductor material layer over and in physical contact with the resistor, wherein a first portion of the etch stop layer is interposed between the first sidewall of the first connector and the semiconductor material layer, and wherein a second portion of the etch stop layer is interposed between the first sidewall of the second connector and the semiconductor material layer.

9. The semiconductor structure of claim 8 , wherein the first portion of the etch stop layer and the second portion of the etch stop layer are in physical contact with the resistor.

10. The semiconductor structure of claim 8 , wherein a topmost surface of the semiconductor material layer is below a topmost surface of the first connector and a topmost surface of the second connector.

11. The semiconductor structure of claim 8 , further comprising a first spacer in physical contact with a second sidewall of the first connector and a first sidewall of the resistor, wherein the second sidewall of the first connector is opposite to the first sidewall of the first connector.

12. The semiconductor structure of claim 11 , further comprising a second spacer in physical contact with a second sidewall of the second connector and a second sidewall of the resistor, wherein the second sidewall of the second connector is opposite to the first sidewall of the second connector, and wherein the second sidewall of the resistor is opposite to the first sidewall of the resistor.

13. The semiconductor structure of claim 8 , further comprising a dielectric layer over the semiconductor material layer, wherein the dielectric layer is interposed between the first portion of the etch stop layer and the second portion of the etch stop layer.

14. The semiconductor structure of claim 13 , further comprising a first contact and a second contact extending through the dielectric layer, wherein the first contact is in physical contact with the first connector, and wherein the second contact is in physical contact with the second connector.

15. A semiconductor structure comprising:
an isolation region extending into a substrate;
a gate dielectric layer over the substrate and the isolation region;
a diffusion barrier layer over the gate dielectric layer, wherein a portion of the diffusion barrier layer forms a resistor;
a semiconductor material layer over the resistor;
a first spacer on a first sidewall of the resistor;
a second spacer on a second sidewall of the resistor, the second sidewall of the resistor being opposite to the first sidewall of the resistor; and
a first connector and a second connector in physical contact with the resistor, the first connector being interposed between the first spacer and the semiconductor material layer, the second connector being interposed between the second spacer and the semiconductor material layer.

16. The semiconductor structure of claim 15 , wherein a width of the resistor is greater than a width of the semiconductor material layer.

17. The semiconductor structure of claim 15 , further comprising a dielectric layer over the semiconductor material layer, wherein a bottommost surface of the dielectric layer is below a topmost surface of the first connector and a topmost surface of the second connector.

18. The semiconductor structure of claim 17 , wherein a topmost surface of the dielectric layer is above the topmost surface of the first connector and the topmost surface of the second connector.

19. The semiconductor structure of claim 15 , wherein a thickness of the semiconductor material layer is less than a height of the first connector.

20. The semiconductor structure of claim 15 , further comprising an etch stop layer, wherein a first portion of the etch stop layer is interposed between the first spacer and the semiconductor material layer, and wherein a second portion of the etch stop layer is interposed between the second spacer and the semiconductor material layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Hua Feng
• Wang Shu-Hui
• Chiang Mu-Chi

Classifications

• H10D84/817

  Combinations of field-effect devices and resistors only · CPC title

• H10D1/47 Primary

  Resistors having no potential barriers · CPC title

• H10D84/209

  of only resistors · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D64/664

  the additional layers comprising a barrier layer between the layer of silicon and an upper metal or metal silicide layer · CPC title