Manufacturing method of via hole, display substrate, and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10872807-B2
Application number	US-201816315406-A
Country	US
Kind code	B2
Filing date	Mar 22, 2018
Priority date	May 12, 2017
Publication date	Dec 22, 2020
Grant date	Dec 22, 2020

Abstract

A manufacturing method of a via hole, a display substrate and a manufacturing method thereof are provided. The manufacturing method of a via hole includes: forming a first via hole penetrating the passivation protection layer, the first via hole being defined by a first side wall of the passivation protection layer; forming an organic insulating layer on the passivation protection layer; and forming a second via hole penetrating the organic insulating layer, the second via hole being defined by a second side wall of the organic insulating layer; wherein in a sectional view, a bottom of the second via hole is located in the first via hole and is in direct contact with the conductive layer, and the second side wall of the organic insulating layer is separated from the first side wall of the passivation protection layer.

First claim

What is claimed is:

1. A manufacturing method of a via hole, comprising:
forming a passivation protection layer on a conductive layer;
forming a first via hole penetrating the passivation protection layer, the first via hole being defined by a first side wall of the passivation protection layer;
forming an organic insulating layer on the passivation protection layer; and
forming a second via hole penetrating the organic insulating layer, the second via hole being defined by a second side wall of the organic insulating layer, wherein
in a sectional view, a bottom of the second via hole is located in the first via hole and is in direct contact with the conductive layer, and the second side wall of the organic insulating layer is separated from the first side wall of the passivation protection layer, wherein a material of the organic insulating layer is a photoresist material,
wherein forming the second via hole penetrating the organic insulating layer comprises: exposing the organic insulating layer by utilizing a first mask; and developing the organic insulating layer thus exposed, to form the second via hole,
the forming the first via hole penetrating the passivation protection layer comprises: coating a photoresist on the passivation protection layer; exposing the photoresist by utilizing a second mask; developing the photoresist thus exposed; etching the passivation protection layer to form the first via hole; and removing the remaining photoresist,
the first mask and the second mask are a same one mask, an amount of light exposure utilized in exposing the organic insulating layer is 80%˜90% of an amount of light exposure utilized in exposing the photoresist, and a material of the organic insulating layer is the same as that of the photoresist.

2. The manufacturing method of the via hole according to claim 1 , wherein the conductive layer is a drain electrode of a thin film transistor of a display substrate.

3. A manufacturing method of a display substrate, comprising the manufacturing method of the via hole according to claim 1 .

4. The manufacturing method of the display substrate according to claim 3 , wherein the conductive layer is a source-drain electrode layer,
before forming the passivation protection layer on the conductive layer, the manufacturing method of the display substrate further comprises:
sequentially forming a gate electrode, a gate insulating layer, an active layer, and the source-drain electrode layer on a base substrate,
after forming the second via hole penetrating the organic insulating layer, the manufacturing method of the display substrate further comprises:
forming a pixel electrode on the organic insulating layer, the pixel electrode being connected to a drain electrode of the source-drain electrode layer through the second via hole;
forming a passivation insulating layer on the pixel electrode; and
forming a common electrode on the passivation insulating layer.

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wan Yunhai
• Yang Chengshao
• Wang Wenlong
• Cao Ke

Classifications

• H10W20/081 Primary

  by forming openings in the dielectric parts · CPC title

• H10D86/443 Primary

  adapted for preventing breakage, peeling or short circuiting · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/0212

  comprising manufacture, treatment or coating of substrates · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title