Information processing device, information processing method, and computer program product

Patent metadata

Field	Value
Publication number	US-10872174-B2
Application number	US-201816117321-A
Country	US
Kind code	B2
Filing date	Aug 30, 2018
Priority date	Mar 20, 2018
Publication date	Dec 22, 2020
Grant date	Dec 22, 2020

Abstract

According to an embodiment, an information processing device operates while switching between a secure mode and a non-secure mode. The information processing device includes processing circuitry. The processing circuitry is configured to function as a switching unit. The switching unit switches a mode from the secure mode to the non-secure mode at the time when the information processing device is operating in the secure mode.

First claim

What is claimed is:

1. An information processing device operating while switching between a secure mode and a non-secure mode, the information processing device comprising:
processing circuitry configured to function as a switching unit, wherein
the switching unit switches a mode from the secure mode to the non-secure mode at a time when the information processing device is operating in the secure mode;
a physical memory; and
a cache memory, wherein
the processing circuitry is configured to further function as a setting unit, and
the setting unit sets, before the mode is switched from the secure mode to the non-secure mode, at least part of a region in the physical memory shared by the secure mode and the non-secure mode to be in a locked state in which data that is written into the cache memory by a first writing unit operating in the non-secure mode is not enabled to be written into the physical memory and is enabled to be read.

2. The device according to claim 1 , wherein
the processing circuitry is configured to further function as a read out unit and a second writing unit,
the read out unit operates in the secure mode, and reads out processing target data that is written into a shared cache region of the cache memory by the first writing unit; and the second writing unit writes, into the physical memory, at least part of the processing target data among pieces of cache data stored in the cache memory before the region is set to be in the locked state by the setting unit.

3. The device according to claim 2 , wherein the setting unit sets, to be in the locked state, at least the region into which the data is written by the second writing unit in a shared physical region corresponding to the shared cache region in the physical memory.

4. The device according to claim 3 , wherein
the second writing unit writes, into the shared physical region of the physical memory, unread data that has not been read by the read out unit among pieces of the processing target data in the cache memory, and
the setting unit sets, to be in the locked state, the region into which the unread data is written in the shared physical region of the physical memory.

5. The device according to claim 3 , wherein
the second writing unit writes, into the shared physical region of the physical memory, the processing target data in the cache memory, and
the setting unit sets, to be in the locked state, the region into which the processing target data is written in the shared physical region of the physical memory.

6. The device according to claim 3 , wherein the second writing unit writes, into the shared physical region of the physical memory, the cache data in the shared cache region in the cache memory.

7. The device according to claim 2 , wherein the second writing unit writes, into the physical memory, all pieces of the cache data in the cache memory.

8. An information processing method executed by an information processing device including processing circuitry, a physical memory, and cache memory and configured to operate while switching between a secure mode and a non-secure mode, the information processing method comprising:
switching a mode from the secure mode to the non-secure mode at a time when the information processing device is operating, in the secure mode, and
setting, before the mode is switched from the secure mode to the non-secure mode, at least part of a region in the physical memory shared by the secure mode and the non-secure mode to be in a locked state in which data that is written into the cache memory by a first writing unit operating in the non-secure mode is not enabled to be written into the physical memory and is enabled to be read.

9. A computer program product comprising a non-transitory computer-readable medium that includes a computer program to be executed by a computer that is executed by an information processing device including processing circuitry, a physical memory, and
a cache memory and configured to operate while switching between a secure mode and a non-secure mode, the computer program causing the computer to perform:
switching a mode from the secure mode to the non-secure mode at a time when the information processing device is operating in the secure mode, and
setting, before the mode is switched from the secure mode to the non-secure mode, at least part of a region in the physical memory shared by the secure mode and the non-secure mode to be in a locked state in which data that is written into the cache memory by a first writing unit operating in the non-secure mode is not enabled to be written into the physical memory and is enabled to be read.

Assignees

• Toshiba Kk

Inventors

• Nara Ryuta
• Kawabata Takeshi

Classifications

• G06F12/0895

  of parts of caches, e.g. directory or tag array · CPC title

• G06F21/74 Primary

  operating in dual or compartmented mode, i.e. at least one secure mode · CPC title

• G06F2212/603

  of operating mode, e.g. cache mode or local memory mode · CPC title

• G06F21/78

  to assure secure storage of data (address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00) · CPC title

• G06F12/0877

  Cache access modes · CPC title