Apparatuses and methods for calibrating adjustable impedances of a semiconductor device

Patent metadata

Field	Value
Publication number	US-10868519-B2
Application number	US-201916505369-A
Country	US
Kind code	B2
Filing date	Jul 8, 2019
Priority date	Dec 9, 2016
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

First claim

What is claimed is:

1. A method, comprising:
arbitrating for use of a common external resistor to avoid conflicts;
performing ZQ calibration to determine calibration results for output driver impedance; and
setting a value in a mode register at completion of the ZQ calibration to indicate if a new calibration result has been determined.

2. The method of claim 1 wherein ZQ calibration is performed on power up.

3. The method of claim 1 wherein the ZQ calibration is a recalibration performed within a time interval.

4. The method of claim 3 wherein the time interval is periodic.

5. The method of claim 1 wherein the ZQ calibration is performed responsive to issuance of a calibration start command.

6. The method of claim 1 , further comprising applying the new calibration results responsive to switching to a new frequency set point.

7. The method of claim 1 , further comprising loading new calibration results into pull-down and pull-up drivers responsive to a latch command.

8. A method, comprising:
arbitrating for use of a common external resistor to avoid conflicts;
performing ZQ calibration to determine calibration results for output driver impedance;
setting a value in a mode register at completion of the ZQ calibration; and
providing the value from the mode register responsive to a mode register read command to notify of new calibration results.

9. A method, comprising:
issuing an impedance calibration start command to a memory to perform impedance calibration operation; and
issuing commands to the memory to change frequency set point and cause the memory to apply calibration results from the impedance calibration operation responsive to changing the frequency set point.

10. A method comprising:
issuing an impedance calibration start command to a memory to perform impedance calibration operation; and
issuing mode register write commands to the memory to change frequency set point and cause the memory to apply calibration results from the impedance calibration operation.

11. The method of claim 9 , wherein applying calibration results from the impedance calibration operation comprises loading calibration values into pull-down and pull-up drivers.

12. The method of claim 9 , further comprising:
issuing a second impedance calibration start command to the memory to perform a second impedance calibration operation; and
issuing a calibration latch command to the memory at a time following the second impedance calibration start command to cause the memory to load calibration results from the second impedance calibration operation.

13. The method of claim 9 , further comprising:
issuing a second impedance calibration start command to a second memory to perform a second impedance calibration operation; and
issuing a calibration latch command to the second memory at a time following the second impedance calibration start command to cause the memory to load calibration results from the second impedance calibration operation.

14. The method of claim 9 , further comprising periodically issuing the impedance calibration start command to the memory to maintain accurate calibration.

15. The method of claim 9 , following power up of the memory, further comprising issuing an earlier calibration latch command before issuing the impedance calibration start command.

16. An apparatus, comprising:
a calibration terminal configured to be coupled to an external resistance;
programmable termination resistances having a programmable impedance; and
an impedance calibration circuit coupled to the calibration terminal and configured to perform a calibration operation to determine calibration results for setting the programmable impedance of the programmable termination resistances based on the external resistance, the impedance calibration circuit further configured to automatically apply the calibration results to the programmable termination resistances responsive to switching to a new frequency set point.

17. The apparatus of claim 16 , further comprising pull-up and pull-down devices, each including respective programmable termination resistances.

18. The apparatus of claim 16 wherein the impedance calibration circuit is further configured to load the calibration results into pull-up and pull-down devices responsive to a calibration latch command.

19. The apparatus of claim 16 wherein the impedance calibration circuit is further configured to arbitrate for control over the external resistance before performing the calibration operation.

20. The apparatus of claim 16 wherein the impedance calibration circuit is configured to perform the calibration operation responsive to a calibration command for command-based calibration and configured to perform the calibration operation without a calibration command for background calibration.

Assignees

• Micron Technology Inc

Inventors

• Gans Dean

Classifications

• H03H11/54

  Modifications of networks to reduce influence of variations of temperature · CPC title

• G11C2207/2254

  Calibration · CPC title

• G11C7/1048 Primary

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C29/022 Primary

  in I/O circuitry · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title