Auto-compensation for control voltage range of VCO at low power supply

Patent metadata

Field	Value
Publication number	US-10868495-B2
Application number	US-201916439662-A
Country	US
Kind code	B2
Filing date	Jun 12, 2019
Priority date	Jun 13, 2018
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

Some aspects of the present disclosure relate to an apparatus, a PLL and an electronic device. The apparatus comprises a voltage-to-current (V2I) converter, a current controlled oscillator and a compensation current. The V2I converter is operable to receive a first voltage and generate a first current based on the first voltage. The current controlled oscillator is coupled to the V2I converter and operable to generate an oscillation signal based on a second current from or to the V2I converter. The compensation circuit is coupled to the V2I converter and operable to receive a third current from or to the V2I converter. The second and third currents vary in response to at least one of temperature variation and supply voltage variation of the apparatus. Variation direction of the third current is opposite to variation direction of the second current and different frequencies may be provided for a low supply voltage domain.

First claim

We claim:

1. An apparatus, comprising:
a voltage-to-current (V2I) converter operable to receive a first voltage (V1) and generate a first current (I1) based on the first voltage (V1);
a current controlled oscillator coupled to the V2I converter, and operable to generate an oscillation signal based on a second current (I2) from or to the V2I converter; and
a compensation circuit coupled to the V2I converter, and operable to receive a third current (13) from or to the V2I converter, wherein the first current (I1) includes a combination of the second and third currents (I2, I3), the second and third currents (I2, I3) vary in response to temperature variation and/or supply voltage (Vdd) variation of the apparatus, and variation direction of the third current (I3) is opposite to variation direction of the second current (I2).

2. The apparatus of claim 1 , wherein the V2I converter comprises:
an operational amplifier (A 0 ) operable to receive the first voltage and a reference voltage, and generate a second voltage (V2) in response to comparison of the first voltage (V1) and the reference voltage (Vref);
a current mirror coupled to the operational amplifier (A 0 ), and operable to receive the second voltage (V2) and generate the first current (I1) and a fourth current (I4), the first current (I1) being a predetermined number of times of the fourth current (I4), and the predetermined number being equal to or greater than 1; and
a reference voltage generator coupled to the current mirror and the operational amplifier (A 0 ), and operable to generate the reference voltage (Vref) based on the fourth current (I4), wherein the reference voltage generator includes a first resistor (R1) or a transistor.

3. The apparatus of claim 2 , wherein the current mirror comprises:
a first transistor unit (PM 1 , NM 1 ) coupled to the reference voltage generator, and operable to generate the fourth current (I4) in response to the second voltage (V2) being applied to a control terminal of the first transistor unit (PM 1 , NM 1 ); and
a second transistor unit (PM 2 , NM 2 ) coupled to the current controlled oscillator, and operable to generate the first current (I1) in response to the second voltage (V2) being applied to a control terminal of the second transistor unit (PM 2 , NM 2 ).

4. The apparatus of claim 3 , wherein
the first transistor unit (PM 1 , NM 1 ) includes a first PMOS transistor (PM 1 ) coupled between the supply voltage (Vdd) and the reference voltage generator,
the second transistor unit (PM 2 , NM 2 ) includes a second PMOS transistor (PM 2 ) coupled between the supply voltage (Vdd) and the current controlled oscillator,
gate width of the second PMOS transistor (PM 2 ) is the predetermined number of times of gate width of the first PMOS transistor (PM 1 ), and
the supply voltage (Vdd) is below 1 V.

5. The apparatus of claim 3 , wherein
the first transistor unit (PM 1 , NM 1 ) includes a PMOS transistor (PM 1 ) coupled between the supply voltage (Vdd) and the reference voltage generator,
the second transistor unit (PM 2 , NM 2 ) includes the predetermined number of second PMOS transistors coupled in parallel between the supply voltage (Vdd) and the current controlled oscillator, and
gate width of each of the predetermined number of second transistor (PM 2 ) equals to gate width of the first PMOS transistor (PM 1 ).

6. The apparatus of claim 3 , wherein
the first transistor unit (PM 1 , NM 1 ) includes a first NMOS transistor (NM 1 ) coupled between the ground (GND) and the reference voltage generator,
the second transistor unit (PM 2 , NM 2 ) includes a second NMOS transistor (NM 2 ) coupled between the ground (GND) and the current controlled oscillator, and
gate width of the second NMOS transistor (NM 2 ) is the predetermined number of times of gate width of the first transistor (NM 1 ).

7. The apparatus of claim 3 , wherein
the first transistor unit (PM 1 , NM 1 ) includes a first NMOS transistor coupled between the ground (GND) and the reference voltage generator,
the second transistor unit (PM 2 , NM 2 ) includes the predetermined number of second NMOS transistors (NM 2 ) coupled in parallel between the ground (GND) and the current controlled oscillator, and
gate width of each of the predetermined number of second NMOS transistors (NM 2 ) equals to gate width of the first NMOS transistor (NM 1 ).

8. The apparatus of claim 1 , wherein the compensation circuit comprises a third PMOS transistor (PM 3 ) coupled between a current mirror and the ground (GND), a gate of the third PMOS transistor (PM 3 ) being coupled to the ground (GND).

9. The apparatus of claim 1 , wherein the compensation circuit comprises a third NMOS transistor (NM 3 ) coupled between a current mirror and the ground (GND), a gate of the third NMOS transistor (NM 3 ) being coupled to the current mirror.

10. The apparatus of claim 1 , wherein the compensation circuit comprises a second resistor (R2), resistance of the second resistor (R2) decreases in response to increasing temperature and/or increasing supply voltage (Vdd) of the apparatus, and the resistance of the second resistor (R2) increases in response to decreasing temperature and/or decreasing supply voltage (Vdd) of the apparatus, and wherein the current controlled oscillator is further operable to generate oscillation signals of different frequencies based on the second current (I2) of different values.

11. The apparatus of claim 1 , wherein the compensation circuit comprises a transistor configured to selectively operate in a saturation region or a sub-threshold region based on a temperature and/or a supply voltage.

12. The apparatus of claim 1 , wherein:
the compensation circuit comprises a transistor;
the supply voltage variation comprises a decrease in a supply voltage; and
in response to the decrease in the supply voltage, the third current decreases, the second current increases, and a threshold voltage of the transistor increases.

13. The apparatus of claim 2 , wherein:
the reference voltage generator comprises the first resistor;
the temperature variation comprises an increase in a temperature; and
in response to the increase in the temperature, a resistance of the first resistor decreases, the second current decreases, and the third current increases.

14. A phase locked loop (PLL) circuit, comprising:
a charge pump generating a first voltage (V1); and
a voltage controlled oscillator coupled to the charge pump and including:
a voltage-to-current (V2I) converter operable to receive the first voltage (V1) and generate a first current (I1) based on the first voltage (V1);
a current controlled oscillator coupled to the V2I converter, and operable to generate an oscillation signal based on a second current (I2) from or to the V2I converter; and
a compensation circuit coupled to the V2I converter and operable to receive a third current (I3) from or to the V2I converter, wherein the first current (I1) includes a combination of the second and third currents (I2, I3), the second and third currents (I2, I3) vary in response to temperature variation and/or supply voltage (Vdd) variation of the apparatus, and variation direction of the third current (I3) is opposite to variation direction of the second current (I2).

15. The circuit of claim 14 , wherein the V2I converter comprises:
an operational amplifier (A 0 ) operable to receive the first voltage (I1) and a reference voltage, and generate a second voltage (V2) in response to comparison of the first voltage (V1) and the reference voltage (Vref);
a current mirror coupled to the operational amplifier (A 0

Assignees

• Lattice Semiconductor Corp

Inventors

• Lei Kai
• Li Shirley
• Wu Oliver

Classifications

• H03B5/04 Primary

  Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature · CPC title

• H03L7/0991

  the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814) · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/183

  a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number {(H03L7/1806 takes precedence)} · CPC title

• H03B5/24

  active element in amplifier being semiconductor device (H03B5/26 takes precedence) · CPC title