Defense techniques for split manufacturing

Patent metadata

Field	Value
Publication number	US-10867937-B2
Application number	US-201815987309-A
Country	US
Kind code	B2
Filing date	May 23, 2018
Priority date	May 23, 2017
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

Disclosed are various embodiments to enhance the security of a circuit design after a global routing of the circuit design and an assignment of wire layers for the circuit design. A tree can be extracted from the circuit design. The tree can include multiple gates and location information for the gates. The tree can be perturbed by moving one or more locations of one or more gates.

First claim

Therefore, at least the following is claimed:

1. A system comprising:
a memory device comprising a circuit design; and
at least one computing device configured to at least:
subsequent to a global routing of the circuit design and an assignment of wire layers for the circuit design, extract a tree from the circuit design, the tree comprising a plurality of gates and a plurality of locations individually corresponding to a respective one of the plurality of gates, the tree being a topology based at least in part on the assignment of wire layers; and
perturb the tree by moving at least one location of the plurality of locations for at least one gate of the plurality of gates.

2. The system of claim 1 , wherein the at least one computing device is further configured to at least:
extract a second tree from the circuit design; and
perturb the second tree.

3. The system of claim 1 , wherein the at least one computing device is further configured to at least:
extract a second tree from the circuit design, the second tree comprising a plurality of second gates;
determine that one of the plurality of second gates has been perturbed previously; and
extract another tree from the circuit design without perturbing the second tree based at least in part on one of the plurality of second gates being previously perturbed.

4. The system of claim 1 , wherein the circuit design corresponds to a flattened circuit design.

5. The system of claim 1 , wherein the tree is perturbed based on at least one of: a placement perturbation technique, a layer elevation technique, a routing detour perturbation technique, and a decoy perturbation technique.

6. The system of claim 1 , wherein the at least one location is selected based at least in part on the at least one gate being part of a dangling wire.

7. The system of claim 1 , wherein the at least one computing device is further configured to perturb the tree by at least ripping up global wire segments; ripping up local nets; generating pseudo pins; performing a driver side detour perturbation; performing a sink side decoy perturbation; and rerouting BEOL wires.

8. A method comprising:
subsequent to a global routing of a circuit design and an assignment of wire layers for the circuit design, extracting, via at least one computing device, a tree from the circuit design, the tree comprising a plurality of gates and a plurality of locations individually corresponding to a respective one of the plurality of gates, the tree being a topology based at least in part on the assignment of wire layers; and
perturbing, via the at least one computing device, the tree by moving at least one location of the plurality of locations for at least one gate of the plurality of gates.

9. The method of claim 8 , further comprising:
extracting, via the at least one computing device, a second tree from the circuit design; and
perturbing, via the at least one computing device, the second tree.

10. The method of claim 8 , further comprising:
extracting, via the at least one computing device, a second tree from the circuit design, the second tree comprising a plurality of second gates;
determining, via the at least one computing device, that one of the plurality of second gates has been perturbed previously; and
extracting, via the at least one computing device another tree from the circuit design without perturbing the second tree based at least in part on one of the plurality of seconds gates being previously perturbed.

11. The method of claim 8 , wherein a pair of gates of the plurality of gates are connected via a wire in a back-end-of-line (BEOL) layer.

12. The method of claim 8 , wherein the circuit design comprises at least one front-end-of-line (FEOL) layers and omits at least one BEOL layer.

13. The method of claim 8 , wherein the at least one location is selected based at least in part on the at least one gate being part of a dangling wire.

14. The method of claim 8 , further comprising generating, via the at least one computing device, a decoy by moving the at least one location to a resulting location in a direction of at least one other gate, the at least one other gate not being directly electrically connected to the at least one gate.

15. A non-transitory computer-readable medium embodying a program that, when executed in at least one computing device, causes the at least one computing device to at least:
subsequent to a global routing of a circuit design and an assignment of wire layers for the circuit design, extract a tree from the circuit design, the tree comprising a plurality of gates and a plurality of locations individually corresponding to a respective one of the plurality of gates, the tree being a topology based at least in part on the assignment of wire layers; and
perturb the tree by moving at least one location of the plurality of locations for at least one gate of the plurality of gates.

16. The non-transitory computer-readable medium of claim 15 , wherein the at least one computing device is further configured to at least:
extract a second tree from the circuit design; and
perturb the second tree.

17. The non-transitory computer-readable medium of claim 15 , wherein the at least one computing device is further configured to at least:
extract a second tree from the circuit design, the second tree comprising a plurality of second gates;
determine that one of the plurality of second gates has been perturbed previously; and
extract another tree from the circuit design without perturbing the second tree based at least in part on one of the plurality of second gates being previously perturbed.

18. The non-transitory computer-readable medium of claim 15 , wherein the circuit design comprises at least one front-end-of-line (FEOL) layers and omits at least one BEOL layer.

19. The non-transitory computer-readable medium of claim 15 , wherein the at least one location is selected based at least in part on the at least one gate being part of a dangling wire.

20. The non-transitory computer-readable medium of claim 15 , wherein the at least one computing device is further configured to at least generate a decoy by moving the at least one location to a resulting location in a direction of at least one other gate, the at least one other gate not being directly electrically connected to the at least one gate.

Assignees

• Univ Texas
• Texas A & M Univ Sys
• Univ Nankai

Inventors

• Rajendran Jeyavijayan
• Hu Jiang
• Wang Yujie
• Chen Pu

Classifications

• H10W42/405

  using active circuits · CPC title

• H10W42/40 Primary

  protecting against tampering, e.g. unauthorised inspection or reverse engineering · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title