Component magnetic shielding for microelectronic devices

Patent metadata

Field	Value
Publication number	US-10867934-B2
Application number	US-201815937542-A
Country	US
Kind code	B2
Filing date	Mar 27, 2018
Priority date	Mar 27, 2018
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

A microelectronic device may include a substrate, a component, a first plate, a second plate, and a shield. The component may be disposed at least partially within the substrate. The first plate may be disposed on a first side of the component. The second plate may be disposed on a second side of the component. The shield may be disposed around at least a portion of a periphery of the component.

First claim

The invention claimed is:

1. A microelectronic device comprising:
a substrate;
a die coupled to the substrate;
a first shielded assembly and a second shielded assembly spaced away from the first shielded assembly, each of the first shielded assembly and the second shielded assembly disposed in the substrate, and first shielded assembly and the second shielded assembly each comprising:
a component located at least partially within the substrate, the component electrically connected to the die;
a first plate disposed on a first side of the component and spaced away from the component;
a second plate disposed on a second side of the component and spaced away from the component, wherein the component is located between the die and the first plate, or between the die and the second plate; and
a shield disposed around a periphery of the component and, together with the first plate and the second plate, to limit transmission of electromagnetic signals to and from the component; and
wherein the shield of the first shielded assembly is located between the component of the first shielded assembly and the component of the second shielded assembly.

2. The microelectronic device of claim 1 , each of the first shielded assembly and the second shielded assembly further comprising:
a conductive element electrically connected to the component and to the die.

3. The microelectronic device of claim 1 , the shield of each of the first shielded assembly and the second shielded assembly further comprising:
an opening in the shield, the conductive element passing therethrough.

4. The microelectronic device of claim 3 , wherein the opening of the shield of the first shielded assembly faces away from the opening of the shield of the second shielded assembly.

5. The microelectronic device of claim 1 , wherein the shield connects to the first plate and the second plate.

6. The microelectronic device of claim 1 , the shield further comprising:
a plurality of vias disposed in the substrate around the component, the plurality of vias substantially surrounding the component and spaced to limit transmission of electromagnetic signals to and from the component.

7. The microelectronic device of claim 6 , wherein the plurality of vias are spaced from each other and from the component to achieve a desired quality factor of the component.

8. The microelectronic device of claim 1 , the shield further comprising:
a substantially continuous shield disposed in the substrate around the component, the wrap substantially surrounding the component to limit transmission of electromagnetic signals to and from the component.

9. A microelectronic device comprising:
a substrate;
a die coupled to the substrate;
a first shielded assembly disposed in the substrate, the first shielded assembly including:
a first component located at least partially within the substrate, the first component electrically connected to the die;
a first plate disposed on a first side of the first component and spaced away from the first component;
a second plate disposed on a second side of the first component and spaced away from the component, wherein the first component is located between the die and the first plate, or between the die and the second plate; and
a first shield disposed around a periphery of the first component and, together with the first plate and the second plate, to limit transmission of electromagnetic signals to and from the first component;

a second shielded assembly disposed in the substrate and spaced away from the first shielded assembly, the second shielded assembly including:
a second component located at least partially within the substrate, the second component electrically connected to the die;
a third plate disposed on a first side of the second component and spaced away from the second component;
a fourth plate disposed on a second side of the second component and spaced away from the second component, wherein the second component is located between the die and the third plate, or between the die and the fourth plate; and
a second shield disposed around a periphery of the component and, together with the first plate and the second plate, to limit transmission of electromagnetic signals to and from the component; and

wherein one or more of the first shield or the second shield are located between the first component and the second component.

10. The microelectronic device of claim 9 , the first shielded assembly further comprising:
a conductive element electrically connected to the first component and to the die.

11. The microelectronic device of claim 9 , wherein:
the first shield includes a first opening with a first conductive element passing through the first opening; and
the second shield includes a second opening with a second conductive element passing through the second opening;
the first conductive element is electrically connected to the first component and to the die; and
the second conductive element is electrically connected to the second component and to the die.

12. The microelectronic device of claim 11 , wherein the first opening faces a first direction and the second opening faces a second direction.

Assignees

• Intel Ip Corp

Inventors

• Maruthamuthu Saravana
• Ort Thomas
• Wolter Andreas
• Augustin Andreas
• Sciriha Veronica
• Waidhas Bernd

Classifications

• H10W90/728

  between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W70/635

  Through-vias · CPC title