Method for manufacturing package structure

Patent metadata

Field	Value
Publication number	US-10867932-B2
Application number	US-202016741001-A
Country	US
Kind code	B2
Filing date	Jan 13, 2020
Priority date	Nov 10, 2016
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

Package structures and methods for forming the same are provided. The method includes forming a redistribution structure embedded in a passivation layer over a carrier substrate and bonding an integrated circuit die to the redistribution structure through first connectors. The method further includes removing the carrier substrate to expose a bottom portion of the redistribution structure and removing the bottom portion of the redistribution structure to form an opening in the passivation layer. The method further includes forming a second connector over the redistribution structure. In addition, the second connector includes an extending portion extending into the opening in the passivation layer.

First claim

What is claimed is:

1. A method for forming a package structure, comprising:
forming a redistribution structure embedded in a passivation layer over a carrier substrate, wherein the redistribution structure comprises a seed layer and a conductive layer over and surrounded by the seed layer;
bonding an integrated circuit die to the redistribution structure through first connectors;
removing the carrier substrate to expose a bottom portion of the redistribution structure;
removing the bottom portion of the redistribution structure to form an opening in the passivation layer, wherein a portion of a sidewall of the passivation layer is exposed through the opening, and a rest of the sidewall of the passivation layer is covered by the seed layer; and
forming a second connector over the redistribution structure, wherein the second connector comprises an extending portion extending into the opening in the passivation layer.

2. The method for forming the package structure as claimed in claim 1 , further comprising:
forming a first package layer surrounding the integrated circuit die and the first connectors before removing the carrier substrate.

3. The method for forming the package structure as claimed in claim 2 , further comprising:
forming a second package layer surrounding the first package layer before removing the carrier substrate,
wherein the second package layer covers a top surface and a sidewall of the passivation layer.

4. The method for forming the package structure as claimed in claim 1 , wherein the first connectors and the second connector are formed at opposite sides of the redistribution structure.

5. The method for forming the package structure as claimed in claim 1 , wherein the opening has a slope sidewall.

6. The method for forming the package structure as claimed in claim 1 , wherein a width of the extending portion of the second connector gradually increases in a direction toward the integrated circuit die.

7. A method for forming a package structure, comprising:
forming a passivation layer having an opening over a carrier substrate;
forming a redistribution layer in the opening of the passivation layer;
disposing an integrated circuit die over a first side of the passivation layer;
forming a first package layer surrounding the integrated circuit die;
forming a second package layer covering a sidewall of the first package layer;
removing the carrier substrate to expose a second side of the passivation layer;
removing the redistribution layer in a first portion of the opening of the passivation wherein a top surface of the redistribution layer facing the second side of the passivation layer is lower than a top surface of the second package layer facing the second side of the passivation layer; and
forming a connector over the redistribution layer, wherein the connector extends into the first portion of the opening.

8. The method for forming the package structure as claimed in claim 7 , wherein a first width of the opening at the first side of the passivation layer is greater than a second width of the opening at the second side of the passivation layer.

9. The method for forming the package structure as claimed in claim 7 , wherein the opening has a slope sidewall, and an upper portion of the slope sidewall is covered by the connector and a bottom portion of the slope sidewall is covered by the redistribution layer.

10. The method for forming the package structure as claimed in claim 9 , wherein the slope sidewall of the opening and a top surface of the second side of the passivation layer form an acute angle.

11. The method for forming the package structure as claimed in claim 7 ,
wherein the first connectors without overlapping an edge portion of the passivation layer.

12. The method for forming the package structure as claimed in claim 11 ,
wherein the second package layer further covers the edge portion of the passivation layer.

13. The method for forming the package structure as claimed in claim 12 , wherein the integrated circuit die is electrically connected to the redistribution layer through conductive bumps.

14. The method for forming the package structure as claimed in claim 13 , wherein the conductive bumps are embedded in the first package layer and are separated from the second package layer.

15. A method for forming a package structure, comprising:
forming a passivation layer having an opening;
forming a redistribution layer in the opening of the passivation layer;
bonding an integrated circuit die to the passivation layer through first connectors;
forming a first package layer around the integrated circuit die and the first connectors;
forming a second package layer covering a sidewall of the first package layer, wherein a portion of the passivation layer overlaps the second package layer but not the first package layer, and the second package layer covers a sidewall of the passivation layer;
removing a portion of the redistribution layer to form an opening in the passivation layer; and
forming a second connector over the redistribution layer, wherein the second connector extends into the opening.

16. The method for forming the package structure as claimed in claim 15 , wherein a sidewall of the second connector is coplanar with a sidewall of the redistribution layer.

17. The method for forming the package structure as claimed in claim 15 , further comprising:
thinning the first package layer and the second package layer to expose the integrated circuit die.

18. The method for forming the package structure as claimed in claim 15 , further comprising:
forming a solder layer over the second connector.

19. The method for forming the package structure as claimed in claim 1 , wherein a top surface of the seed layer is level with a top surface of the conductive layer after removing the bottom portion of the redistribution structure.

20. The method for forming the package structure as claimed in claim 3 , wherein a bottom surface of the second package layer is level with a bottom surface of the passivation layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Yi-Da
• Lin Cheng-Ping
• Lin Wei-Hung
• Lin Chih-Wei
• Cheng Ming-Da
• Hsieh Ching-Hua
• Liu Chung-Shi

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/0198

  batch processes · CPC title